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Objective To investigate the case of a child infected with coronavirus disease 2019 (COVID-19) who had subsequent viral reactivation. Methods We retrospectively analyzed the clinical manifestations, epidemiological data, laboratory and imaging examinations, treatment, and follow-up of the child. And then, we searched related literature using PubMed. Results The 9-year-old boy was exposed to COVID-19 in Malawi and tested positive for NAT in Haikou, China. He was asymptomatic and admitted to our hospital. After six negative NATs, he was discharged from the hospital and quarantined in a hotel. His infection was reactivated again after 22 days (interval between first and last positive NATs). The cycle threshold (Ct) values of positive tests were 25 and 31, and the gene sequencing viral loads were very low. The viral strain Kenya/P2601/2020, a variant of the hCoV-19/Wuhan/IVDC-HB-01/2019 genome (GISAID accession IL: EPI_ISL_402119), was found when polymerase chain reaction enrichment was used to sequence the virus. However, people around him tested negative for COVID-19. Conclusion First, we confirmed the reactivation of COVID-19 in a child. The risk of recurrent infection with SARS-CoV-2 was low, and the policy of strictly isolating patients carrying long-term viral ribonucleic acid should be reconsidered. The interval positivity was most likely due to incorrect sampling and/or testing methods. SGS and aB testing are recommended for children with viral reactivation. Second, SARS-CoV-2 viral reactivation cannot be ruled out. The possible mechanisms, such as prolonged infection and viral latent reactivation, need further investigation.

Objective To investigate the clinical characteristics, epidemiological characteristics, and transmissibility of coronavirus disease 2019 (COVID-19) in a family cluster outbreak transmitted by a 3-month-old confirmed positive infant. Methods Field-based epidemiological methods were used to investigate cases and their close contacts. Real-time fluorescent reverse transcription polymerase chain reaction (RT-PCR) was used to detect Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-CoV-2) for all collected specimens. Serum SARS-CoV-2 IgM and IgG antibodies were detected by Chemiluminescence and Gold immnnochromatography (GICA). Results The outbreak was a family cluster with an attack rate of 80% (4/5). The first case in this family was a 3-month-old infant. The transmission chain was confirmed from infant to adults (her father, mother and grandmother). Fecal tests for SARS-CoV-2 RNA remained positive for 37 days after the infant was discharged. The infant’s grandmother was confirmed to be positive 2 days after the infant was discharged from hospital. Patients A (3-month-old female), B (patient A’s father), C (patient A’s grandmother), and D (patient A’s mother) had positive serum IgG and negative IgM, but patients A’s grandfather serum IgG and IgM were negative. Conclusion SARS-CoV-2 has strong transmissibility within family settings and presence of viral RNA in stool raises concern for possible fecal–oral transmission. Hospital follow-up and close contact tracing are necessary for those diagnosed with COVID-19.

Hypoxia and high-fat diet (HFD) feeding are two factors commonly existing in aquaculture. However, their individual and combined effects on nutrient composition and flesh quality in fish have not been investigated. The present study evaluated the alterations of growth, nutrient composition and flesh quality in Nile tilapia (initially 7.0 ± 0.1 g and 5.6 ± 0.2 cm) fed with normal fat diet (5.95% fat) or HFD (11.8% fat) at two dissolved oxygen levels (1.1 ± 0.1 and 7.2 ± 0.1 mg/L) for 8 weeks. The results showed that hypoxia and HFD had similar effects in inducing lipid deposition, reducing flesh protein and amino acids content, pH values and water holding ability. Hypoxia had additional adverse effects in decreasing meat yield, flesh contents of n-3 PUFA and glycogen, increasing flesh fragmentation and causing liver damages. The combination of hypoxia and HFD significantly decreased feed intake, survival rate and muscle protein content, but didn’t affect flesh quality-related parameters.

To investigate the relationship between the levels of plasma adrenaline and norepinephrine and gene polymorphism of β1 adrenergic receptor G1165C in children with enterovirus 71 (EV71) infection in hand foot and mouth disease (HFMD).The polymerase chain reaction (PCR) was used to detect the expression of gene polymorphism of β1 adrenergic receptor G1165C in vitro. The levels of plasma adrenaline and norepinephrine were measured by enzyme-linked immunosorbent assay (ELISA).The plasma norepinephrine level of severe group was significantly higher than the mild group in children with EV71 infection in HFMD (P 0.05); however, the levels of plasma adrenaline in two groups had no statistical differences (P 0.05); There was no significant difference in the distribution of β1 adrenergic receptor G1165C genotype and allele between EV71 infection group and healthy control group (P 0.05). Further analysis of EV71 infection group by dividing it into mild and severe groups showed that there was no significant difference in the distribution of genotype and allele between these two groups as well (P 0.05). There was no significant difference in the levels of epinephrine and norepinephrine in different genotypes of EV71 infection group (P 0.05), and in the levels of plasma epinephrine and norepinephrine in the mild and severe groups (P 0.05).As the disease gets worse, the plasma norepinephrine level has a rising trend in children with EV71 infection in HFMD, which is an important indicator to evaluate the progress of the disease. However, the gene polymorphism of β1 adrenergic receptor G1165C have no significant correlation, not only with the susceptibility and severity of EV71 infection in hand, foot and mouth disease, but also with the levels of catecholamine.

A low power supply sample-and-hold circuit for a pipelined analog-to-digital converter is described. Several approaches have been used to reduce the power consumption, including a gain-compensated structure and a simple optimum allocation of settling time parameter. To reduce the nonlinear error of the sampling switch, a signal dependent clock bootstrapping system is used. Simulation results demonstrate that the S/H circuit consumes only 2.3 mWat 1.8v supply with an accuracy of 10bit and a sampling rate of 50M

An automatic calibration technique is developed to trim the differential OPAMP's input-referred and its former output stage offset voltages. The offset voltage is reduced by digitally adjusting the resulting offset current at the input and its first output stage. Without using complex circuits, the technique just need a comparator, a simple control logical and a current DAC (I-DAC). The proposed circuits have been designed in a 0.25 mum digital CMOS process. The OPAMP can calibrate a maximum offset of plusmn6 mV. The measured input referred offset voltage is less than 100 muV

The nano-fabrications are playing an ever-increasing role in science and technology research. The electron beam lithography is the key technology to realize nano-fabrication. Electron beam lithography and structure of e-beam system are introduced in this paper. Some key technology such as the proximity effect correction, resist process, and mix & match lithography are investigated. The 0.1 /spl mu/m GaAs PHEMT devices and 36nm CMOS device are successfully achieved by combining the above technology.

In this paper, a novel fully differential gain-boosted telescopic cascode opamp is analyzed and designed. The main op amp is a fully differential telescopic op amp and has a switched capacitor CMFB circuit. The boosting op amp is a fully differential folded cascode op amp and has a continuous time CMFB circuit. The op amp is designed in SMIC 0.35/spl mu/m mixed-signal CMOS process with 3.3 v power supply and achieved a dc gain of 129dB with a 161MHz unity gain frequency.

A novel method of asynchronous data-path average performance analysis is described. This method is based on multi-delay modeling, SPICE and logic simulation. It provides an effective tool to design and analysis asynchronous data-paths. According to the proposed procedure, the performance of an asynchronous 4-bit and 8-bit comparator is analyzed.

A novel asynchronous data-path design is described. Circuits for the asynchronous adder unit, asynchronous comparator unit, and asynchronous selector unit are proposed. An asynchronous data-path ACS (add-compare-select) for a Viterbi decoder is formed. The performance of the 4-bit ACS is analyzed with a novel method based on a multi-delay model. The results of performance analysis of the asynchronous 4-bit ACS show that the average case response time of 6.81 ns is only 84% of the worst-case response time, 8.08 ns. It reveals that the asynchronous data-path has some performance advantages over the synchronous one.

Recently, turbo code has gathered much attention for its outstanding performance. Many literatures have been published on algorithm and applications of turbo code. However, there is little progress on the decoding mechanism of turbo decoder. In this paper we propose an asymmetry AWGN (additive white Gaussian noise channel) model. The proposed model simplified the turbo decoder to an RSC decoder. Through the simulation of the proposed model, two mechanisms of the TURBO decoder have been uncovered. First, turbo decoder improves the S/N (signal to noise) rate of systematic code. Second, turbo decoder improves affection of the systematic code. The simulation result shows that the proposed model is consistent with turbo decoder

In this paper, we present a new asynchronous ACS (adder-compare-select) unit, which is a key building block in the Viterbi decoder. Asynchronous self-timed control and DCVSL (Differential Cascade Voltage Switch Logic) have been used in the ACS unit. The simulation results show that the average case response time 3.51ns is only 42.6% the worst case response time 8.23ns. This explains that the asynchronous ACS unit has performance advantage over the synchronous one.

A novel asynchronous ACS (Add-Compare-Select) is described. The circuit of a novel asynchronous comparator unit is proposed. The performance of ACS is analyzed with the novel method based on multi-delay model. The results of performance analysis of asynchronous ACS show that the average case response time 3.66ns is only 45% the worst-case response time 8.1ns. It reveals that the asynchronous ACS has some performance advantages than the synchronous one.

In this paper we design an analog multiplier by the MOS transistors working in the subthreshold mode. Using the multiplier as the core circuit, we design a family of modules which can compute the probability by the current. On the basis of these modules, the pipelining serial-to-parallel interface, and the maximum a posteriori probability (MAP) algorithm, we implement a novel soft-decision analog probability decoder of the (5,2,3) trellis code. With the standard 0.6 mm CMOS technology we simulate and verify the analog decoder.

This paper presents a novel 1.5 V BiCMOS logic structure (BiCDMOS), in which N-channel depleted MOS transistor (NDMOS) is employed. This does not make the standard BiCMOS technology more difficult. In the BiCDMOS circuit, NDMOS transistor is used and it makes the design more flexible, with less area, and it shortens the path from the input to the output to improve the operation speed.

Due to the rapid expansion of the application areas of digital signal processing (DSP), various fast multiplication-and-accumulation (MAC) modules are required by system developers. In this paper, a high speed and random logic structure MAC design methodology is presented with Wallace trees and borrow-select subtracters (BSSs) as the architecture of the MAC. EDA tools can be utilized to perform automatic placement and routing. A 16*12 MAC and a complex 16*12 MAC with both real and imagine parts are designed by applying this methodology for a 1-million-transistor DSP chip. Simulation results of the modules in 0.6 /spl mu/m CMOS technology are encouraging.

In this paper, a method considering CFG's effect on the costs of sub-graph matching based HW/SW system is proposed. First, a discussion of all kinds of effects generated by CFG in sub-graph matching based co-design is made. Next, an algorithm called "Grade Every Sub-Graph of a DFG According to Its Execution Frequency Decided by CFG" (GESG) is proposed unifying all these effects. At last, delay cost function of sub-graph matching based HW/SW system is modified according to GESG. Experiments and their results are reported and discussed.

A new low power bootstrapped adiabatic logic circuit, Complement Pass-Transistor Bootstrapped Charge-Recovery Logic (CP-BCRL), is presented. CP-BCRL has more efficient energy transfer and recovery due to using the bootstrap technique and adiabatic logic. It consumes less energy and is insensitive to output load capacitance. The HSPICE simulation result is given which use the 0.6-um CMOS technology.

A novel method of asynchronous data-path performance analysis is described. This method is based on multi-delay modeling and SPICE and logic simulation. It provides an effective tool to design and analyse asynchronous data-path. According to the proposed procedure, the performance of an asynchronous ACS is analyzed.

A prototype of a single chip AWG was presented. The system., implemented on a Virtex-E FPGA, included a 32 bits phase accumulator, 8 k/spl times/13 bits waveform lookup table (WLT) and a parabolic interpolation filter. The sample rate of the system is over 100 MSPS.

In this paper, the comparison of the jitter performances and the spurious tones between DLL (Delay Locked Loop) and PLL based RF CMOS oscillators is produced. An equation which offers the evaluation of the strength of the spurious tones due to the current mismatches in charge pumps of DLL based RF CMOS oscillators is offered. By the jitter performance comparison between the PLL and DLL, some suggestions are made for the choice of an oscillator structure between DLL and PLL based oscillators fabricated in CMOS processes to get an optimum jitter performance and power consumption.