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Owing to the superior performances, silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfets) attract a lot of attention. To increase the power density, it is desired to use the third quadrant (3rd-quad) characteristics of the mosfet rather than the externally paralleled Schottky diode for freewheeling during the deadtime. It has been known that the 3rd-quad is far more than a body diode, and the MOS channel is also an important part of it. The channel may be not fully closed and, therefore, play a significant role in the reverse conduction even when the gate is zero or negatively biased. However, a comprehensive study of the 3rd-quad characteristics is still to be conducted. In this article, experiments and simulations are conducted and a physical model is developed to explain the 3rd-quad characteristics of the SiC mosfet. It reveals how and why the 3rd-quad characteristics are affected by the gate voltage and the junction temperature. This article is helpful for not only the application of SiC mosfet but also the device design. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) are widely used in grid scale power electronics. Due to the presence of a dc component in the arm current, the MMC submodules (SMs) show an unbalanced current loading profile. This may lead to some semiconductor chips being more stressed than others, significantly affecting the overall reliability. To level the junction temperatures and improve the SM reliability, this article proposes an asymmetrical power module design in line with the loading profile, allocating more chips to higher current parts. This is shown to be realistic if the power flow is unidirectional. The concept is investigated using simulation backed by experiment. It is shown that the designed power module can significantly reduce the maximum temperature and the total power loss can be reduced by 5%–8%. The chip utilization rate is also improved. The proposed module is applicable in a certain range of power factor and modulation index adjustment. This article provides a guidance for optimum design of the power module for the SMs in an MMC. [ABSTRACT FROM AUTHOR]

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off-state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off-state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications. [ABSTRACT FROM AUTHOR]