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Abstract The continued downscaling of silicon CMOS technology presents challenges for achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily integrated into existing fabrication lines is required. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased to 850 µS/µm by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The potential of the material system for a future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.

Epitaxy of semiconductor-based quantum well structures is a challenging task since it requires precise control of the deposition at the submonolayer scale. In the case of Ge1–xSnx alloys, the growth is particularly demanding since the lattice strain and the process temperature greatly impact the composition of the epitaxial layers. In this paper, the realization of high-quality pseudomorphic Ge1–xSnx layers with Sn content ranging from 6 at. % up to 15 at. % using isothermal processes in an industry-compatible reduced-pressure chemical vapor deposition reactor is presented. The epitaxy of Ge1–xSnx layers has been optimized for a standard process offering a high Sn concentration at a large process window. By varying the N2 carrier gas flow, isothermal heterostructure designs suitable for quantum transport and spintronic devices are obtained.

The continued downscaling of silicon CMOS technology faces big challenges in achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, to date a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily integrated into existing fabrication lines is still missing. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET performance is improved by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The very high potential of the material system for future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.

Harvesting the full potential of single-crystal semiconductor nanowires (NWs) for advanced nanoscale field-effect transistors (FETs) requires a smart combination of charge control architecture and functional semiconductors. In this article, high-performance vertical gate-all-around NW p-type FETs (p-FETs) are presented. The device concept is based on advanced Ge0.92Sn0.08/Ge group IV epitaxial heterostructures, employing quasi–one-dimensional semiconductor NWs fabricated with a top-down approach. The advantage of using a heterostructure is the possibility of electronic band engineering with band offsets tunable by changing the semiconductor stoichiometry and elastic strain. The use of a Ge0.92Sn0.08 layer as the source in GeSn/Ge NW p-FETs results in a small subthreshold slope of 72 mV/dec and a high ION/IOFF ratio of 3 × 106. A ∼32% drive current enhancement is obtained compared to the vertical Ge homojunction NW control devices. More interestingly, the drain-induced barrier lowering is much smaller with GeSn instead of Ge as the source. The general improvement of the transistor’s key figures of merits originates from the valence band offset at the Ge0.92Sn0.08/Ge heterojunction, as well as from a smaller NiGeSn/GeSn contact resistivity.

In this article, vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top–down approach are demonstrated. Thanks to optimized dry etching and digital etching, high-performance Ge GAA nanowire pFETs show low subthreshold swing (SS) of 66 mV/dec, small DIBL, and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $> 10^{{6}}$ . The impact of nanowire diameter scaling from 65 to 20 nm on the key electrical figures of merit (FOMs) of vertical nanowire devices is investigated. The devices with 65-nm diameters show the highest ${I}_{ \mathrm{\scriptscriptstyle ON}}$ and peak transconductance ${G}_{\text {max}}$ due to reduced total resistance $R_{\text {tot}}$ , while the smallest diameter devices yield the largest ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratios and the smallest DIBL due to strong gate electrostatics. The source/–drain asymmetry inherently exists in the vertical nanowire architectures. By swapping the source and drain, electrical FOMs keep the similar trend in diameter scaling. ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , ${R}_{\text {tot}}$ , and ${G}_{\text {max}}$ asymmetry can be attributed to top–bottom contact resistance difference resulting from the doping deactivation effect in small nanowires.

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.

In this paper we present an experimental study of SOI UTBB n-MOSFETs at cryogenic temperatures. The device employs fully silicided source/drain with dopant segregation formed by “Implantation Into Silicide” (IIS) process. The impact of the back-gate (Vback) on the device performance is systematically investigated. The results demonstrate that Vback is essential to tune the threshold voltage Vth. And optimization of Vback values can improve the subthreshold swing (SS), Drain-Induced Barrier Lowering (DIBL), transconductance Gm and mobility at cryogenic temperatures, providing a potential to fulfill the ultra-low power requirement for quantum computing application.

Neuromorphic computing inspired by the neural network systems of the human brain enables energy efficient computing for big-data processing. A neural network is formed by thousands or even millions of neurons which are connected by even a higher number of synapses. Neurons communicate with each other through the connected synapses. The main responsibility of synapses is to transfer information from the pre-synaptic to the postsynaptic neurons. Synapses can memorize and process the information simultaneously. The plasticity of a synapse to strengthen or weaken their activity over time make it capable of learning and computing. Thus, artificial synapses which can emulate functionalities and the plasticity of bio-synapses form the backbones of neuromorphic computing. Alternative artificial synapses have been successfully demonstrated. The classical two-terminal memristor devices, like resistive random access memory (ReRAM), phase change memory (PCM) and ferroelectric tunnel junctions (FTJs) with one terminal connected to the pre-synaptic neuron and another connected with the post-synaptic neuron, own advantages of simple structure, easy processing with high density, and capability of integration with CMOS. However, signal processing and learning cannot be performed simultaneously in 2-terminal devices, thus limiting their synaptic functionalities. Ferroelectric field effect transistors (FeFET) which uses ferroelectric as the gate oxide are the most interesting three-terminal artificial synapse devices, in which the gate or the source is connected to the pre-synaptic neuron while the drain is used for the terminal of the post-synaptic neuron , thus can perform signal transmission and learning simultaneously. However, traps at the channel interface can degrade the device performance causing low endurance. Focuses of those abovementioned devices have been mainly put on the homosynaptic plasticity, which is input specific, meaning that the plasticity occurs only at the synapse with a pre-synaptic activation . The homosynaptic plasticity has a drawback of positive feedback loop: when a synapse is potentiated, the probability of the synapse to be further potentiated is increased. Similarly, when a synapse is depressed the probability of the synapse of being further depressed is higher. Therefore, synaptic weights tend to be either strengthened to the maximum value or weakened to zero, causing the system to be unstable. In contrast, heterosynaptic plasticity can be induced at any synapse at the same time after episodes of strong postsynaptic activity, avoiding the positive feedback problem and stabilize the activity of the post-synaptic neuron. To address the above challenges we proposed a very simple 4-terminal synapse structure based on gated Schottky diodes on silicon (FEMOD) with a ferroelectric layer. The conductance of the Schottky diode is modulated by the polarization of the ferroelectric layer. With this simple synapse structure we can achieve multiple hetero-synaptic functions, including excitatory/ inhibitory post-synaptic current (EPSC/IPSC), paired-pulse facilitation/depression (PPF/PPD), long-term potentiation/depression (LTP/LTD), as well as biological neuron-like spike-timing-dependent plasticity (STDP) characteristics. The modulatory synapse can modify the weight of another synapse with a very low voltage. Furthermore, logic gates, like AND and NAND which are highly desired for in-memory computing can be realized with such simple structure. Figure 1

The experimental demonstration of Ge1-xSnx alloys lasers opened group-IV materials towards high-performance electronic and photonic devices that can be easily integrated with the current Si semiconductor technology. In recent years, GeSn-based optoelectronic devices including light-emitting and detectors, modulators, and CMOS have been proven. The major challenges for the Ge1-xSnx epitaxy arise from the low solid solubility of Sn in Ge, the large lattice mismatch, and the reduced thermal stability between Ge and Sn. All these are becoming extremely critical at higher Sn contents. Non-equilibrium conditions offered by molecular beam epitaxy (MBE), chemical vapor deposition (CVD), flash lamp, or laser annealing have been lately investigated. Between them, CVD is to date the preferred growth technique for its current development compatible with the industry offering micron-thick layers with the highest crystal quality. While Tin-tetrachloride (SnCl4) becomes the standard Sn precursor, for Ge different gasses, like germane (GeH4) and digermane (Ge2H6) are used attempting to archive high Sn incorporation and high material quality. While Ge1-xSnx films with the same high Sn content can be obtained regardless of the used precursor, the advantages and disadvantages of each precursor are discussed in this work. The use of Ge2H6 is accompanied by high growth rates, being favorable in applications where relatively thick films are needed, such as laser structures. On the other hand, with a relatively low growth rate, GeH4 provides a greater thickness control, achieving clear and sharp interfaces in heterostructures. For this reason, GeH4 is the appropriate precursor for quantum transport or spintronic. The biggest challenge in heterostructure designs is going up and down in Sn content. The growth of a Ge1-ySny on a Ge1-xSnx, y1-xSnx alloys. In this work, we address simple methodologies to enhance the gradient or step Sn content without changing the process temperature. Controlling only the carrier gas flow while keeping the standard growth parameters constant, high-quality Ge1-xSnx alloys with uniform Sn content up to 15 at.% are obtained. The proposed method acts as guidance to produce Ge1-xSnx heterostructures that can be extended to any CVD reactor, independently of the used precursor, GeH4 or Ge2H6. Different devices structures are presented proving the applicability of the isothermal multilayer growth. Figure 1

In this paper we present an experimental investigation on SOI UTBB n-MOSFETs at cryogenic temperatures. The device has a silicide source/drain with dopant segregation formed by "Implantation Into Silicide" (IIS) process. The controllability of the back-gate (V back ) on the device performance is characterized, showing that Vback is essential to tune the threshold voltage Vth and improve the subthreshold swing SS, Drain-Induced Barrier Lowering DIBL and mobility at cryogenic temperatures. The cryogenic effect on V th , SS and DIBL with different V back is also studied. Furthermore, using the V back and quantization effect at cryogenic temperature, we can optimize the SS to a lower value, providing a potential way to get ideal value of SS at cryogenic temperature.

Steep slope negative capacitance MOSFETs with HfYOx ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon because a strong polarization switching is needed for the steep slope. We found that the sub-thermal SS degrades with the cycling measurements, which is assumed to be caused by the trap charging in the ferroelectric oxide layer. The tradeoff between polarization and charge trapping is responsible for the subthreshold behavior of the device.

The gate–source overlap length ( ${L}_{{\text {OV}}}$ ) in the line tunneling FET (L-TFET) can be used as a design parameter to improve the analog circuit performance. In this paper, we investigate the drain current ( ${I}_{D}$ ) dependence on ${L}_{{\text {OV}}}$ , considering the electrostatics of the gate–source overlap region. It is observed that ${I}_{D}$ increases with ${L}_{{\text {OV}}}$ exhibiting a nonlinear behavior. This happens as the impact of the lateral electric field at the far end of the tunnel junction reduces, thereby reducing the tunneling rate. Based on our semiempirical physical ${I}_{D}$ – ${L}_{{\text {OV}}}$ model, a novel ${L}_{{\text {OV}}}$ variation-aware small signal model for L-TFET is also proposed. The output resistance and the gate–drain capacitance remain almost independent of ${L}_{{\text {OV}}}$ in the saturation regime. The gate–source capacitance and the transconductance linearly increase with ${L}_{{\text {OV}}}$ . A common source amplifier is demonstrated with ~2.4 times increase in the voltage gain when ${L}_{{\text {OV}}}$ is increased from 20 to 50 nm, with a penalty of ~10% in the bandwidth. We observe that it is not possible to achieve the gain similar to one obtained using 2.5 times increase in ${L}_{{\text {OV}}}$ even after increasing the device width five times. However, the bandwidth reduces 30% at such width owing to an increase in the gate capacitances.

We present a novel T-shaped tunneling field-effect transistor (TFET) on Si-on-insulator (SOI). The asymmetric source-drain structure can effectively suppress the ambipolar switching. The on-current ( $\text{I}_{\mathrm{ on}}$ )/off-current ( $\text{I}_{\mathrm{ off}}$ ) ratio reaches very high value of $\sim 10^{8}$ at $\text{V}_{\mathrm{ ds}}= - 0.5$ V with a smaller tunneling junction width at the drain. The innovative T-shape design allows integration of both TFET and metal-oxide semiconductor field-effect transistors (MOSFET) operation modes in one structure. Both TFET and MOSFET operation modes are experimentally demonstrated in this device structure, which provide the implementation of the selector function with the single device.

This paper presents the derivation of a compact dc modeling approach for the band-to-band tunneling current in double-gate tunnel-field effect transistors (TFETs). The physics-based model equations are solved in closed form by including 2-D effects and are implemented in the hardware description language Verilog-A. The verification of the model is done in two steps. First, the modeling approach is verified by TCAD Sentaurus simulation data of the band diagram, the transfer current, and the output current characteristics as well as the output conductance. The modeling results show a good agreement with the TCAD data. Then, measurement data of complementary nanowire gate-all-around TFET devices are utilized to verify the model and to show possible fields of application. As a part of the verification, the benefits and limitations are analyzed and discussed. The numerical stability and flexibility of the model are pointed out by performing simulations of a single-stage TFET inverter.

Neuromorphic computing inspired by neural network systems of the human brain enables energy efficient computing as a solution of the von Neumann bottleneck. A neural network consists of thousands or even millions of neurons which communicate with each other through connected synapses. Synapses can memorize and process the information simultaneously. The plasticity of a synapse to strengthen or weaken its activity over time make it be capable of learning and computing. Thus, artificial synapses which can emulate functionalities and the plasticity of bio-synapses form the backbone of a neuromorphic computing system. Non-volatile memories with two-terminals, like resistive random-access memory (ReRAM), phase change memory (PCM), are attractive candidates for artificial synapses. However, signal processing and learning cannot be performed simultaneously in these two-terminal synapses. FeFET, similar to a MOSFET structure using CMOS compatible HfO2 based ferroelectrics as gate oxide forms three-terminal synapses offering high endurance, good performance and high energy efficiency. In contrast to two-terminal devices, three terminal FeFET based synapses can perform processing and learning at the same time. In order to maintain the ferroelectric properties of an HfO2 based ferroelectric film, high temperature annealing should be avoided after the ferroelectric layer deposition. In this paper, we present ferroelectric NiSi2 source/drain Schottky barrier (SB) MOSFET (FE-SBFET) structure (Fig.1a), which requires neither ion implantation nor thermal activation of source/drain contacts at high temperatures. FE-SBFETs were fabricated on SOI substrates with a boron-doped (1016 B/cm-3), 55 nm thick top Si layer and a 145 nm thick buried oxide (BOX) layer. Very thin (9 nm) single crystalline NiSi2 layers which offer superior properties of uniform and stable SB contacts on Si are used at source/drain regions. A gate stack consisting of 10 nm thick Hf0.5Zr0.5O2 (HZO) layer and a 40 nm thick TiN layer are deposited by ALD and sputtering, respectively. A rapid thermal annealing at 500 °C is performed to crystallize the HZO into a ferroelectric phase before the gate patterning. The fabricated device has a channel length of 10 µm and a gate width of 10 µm. The overlap between the top gate and NiSi2 is 6 µm along the channel and 10 µm wide on each side. The ferroelectric polarization modulates both the SB at the source/drain contacts as well as the potential in the channel, thus changing the carrier injection through the SB. The Id-Vg transfer characteristics of a p-type FE-SBFET shows a clockwise hysteresis which is caused by the ferroelectric polarization switch. The excitatory post-synaptic current (EPSC), one of the typical short-term synaptic plasticity features for biologic synapses, is characterized by measuring the transient drain currents for a voltage pulse on the gate of a FE-SBFET (Fig.1b). The amplitude of the pulse VAM changes from -0.2 to -1.2 V with a fixed pulse width tpw=1 μs. We found that the EPSC peak value increases linearly with VAM. It shows a very low energy/spike consumption of 2fJ/spike at VAM=-0.2 V, demonstrating a very high energy efficiency. From the EPSC measurements with repeated gate voltage pulses paired-pulse facilitation/depression (PPF/PPD) are characterized showing an exponential decay, similar to biological synapses. The long-term synaptic plasticity of FE-SBFET synapses is characterized by a series repeated identical or non-identical pulses. The later can improve the long-term potentiation/depression (LTP/LTD) symmetry and linearity. The measurements show a large Gmax/Gmin ratio, very high endurance and small cycle-to-cycle (CTC) variation (1.06%) due to the perfect contact of NiSi2 (Fig.1c). The biological neuron-like spike-timing-dependent plasticity (STDP) is characterized for the FE-SBFET synapse. The results show an asymmetric anti-Hebbian STDP, which is one of the biological STDP functionalities (Fig.1d). In conclusion, the fabricated FE-SBFET synapse exhibits multiple synaptic functions with high endurance and small variations. The ultra-low energy/spike consumption indicates a high potential for low power neuromorphic computing applications. Acknowledgement: This work was supported by the Federal Ministry of Education and Research (BMBF, Germany) in the project NEUROTEC (16ME0398K). Figure 1

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this Abstract, we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys. On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added. The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel. These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics. Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”. References: [1] M. Liu et al. ACS Appl. Nano Mater. 4, 94-101 (2021) [2] S. Wirths et al. Nature Photonics 9, 88-92 (2015) [3] J. Kouvetakis, J. Menendez, A. V. G. Chizmeshya: Annu. Rev. Mater. Res. 36:497-554 (2006) Figure 1

We demonstrate high performance vertical heterojunction Ge0.92Sn0.08/Ge gate-all-around (GAA) nanowire (NW) pMOSFETs enabled by a top-down approach, a self-limiting digital etching and NiGeSn metallization. Thanks to the GAA NW geometry and EOT scaling, low SS of 67 m V /dec, small DIBL of 24 m V/ V, and a high $\mathrm{I}_{\mathrm{ON}}/\mathrm{I}_{\mathrm{OFF}}$ ratio of ~ 10 6 are achieved in the smallest NW device with a diameter down to 25 nm. Furthermore, record high $\mathrm{G}_{\mathrm{m},\mathrm{ext}}$ of ~870 $\mu \mathrm{S}/\mu \mathrm{m}$ and the best quality factor $\mathrm{Q}=\mathrm{G}_{\mathrm{m},\mathrm{ext}}\mathrm{SS}_{\mathrm{sat}}$ of 9.1 are obtained for all reported GeSn-based pFETs.

We present a systematic study on the effects of CF

We present a systematic study on the effects of CF4 plasma immersion ion implantation (PIII) in Si on the phase evolution of ultra-thin Ni silicides. For 3 nm Ni, NiSi2 was formed on Si substrates with and without CF4 PIII at temperature as low as 400 °C. For 6 nm Ni, NiSi was formed on pure Si, while epitaxial NiSi2 was obtained on CF4 PIII Si. The incorporation of C and F atoms in the thin epitaxial NiSi2 significantly reduces the layer resistivity. Increasing the Ni thickness to 8 nm results in the formation of NiSi, where the thermal stability of NiSi, the NiSi/Si interface and Schottky contacts are significantly improved with CF4 PIII. We suggest that the interface energy is lowered by the F and C dopants present in the layer and at the interface, leading to phase evolution of the thin Ni silicide.

The subthreshold behavior of floating-gate MOSFETs connected with ferroelectric capacitors (FeCs) was investigated experimentally and theoretically. We found that the subthreshold swing (SS) decreases with decreasing ferroelectric capacitance (i.e., with the decreasing FeC area), in contrast to the voltage dividing effect of regular dielectric capacitors. The ferroelectric polarization switching counteracts the effect of voltage dividing by introducing an additional charge onto the floating gate, which improves the SS and leads to the observed SS dependence. The SS improvement caused by the polarization switching is different from the negative capacitance effect, which is helpful to further understand the ferroelectric transistor.

In this paper, we propose a recessed-gate tunneling field-effect transistor (TFET) to improve the on current of TFETs by increasing the tunnel area with line tunneling. We investigate the effects of the recessed-body thickness and the doping level on the device performance. For optimal device structures, our proposed n-TFET reaches $1.44 \times 10^{-6}$ A/ $\mu \text{m}$ of on current and $3.22 \times 10^{9}$ ON/ OFF current ratio. A minimum subthreshold swing SS $_{{\textsf {min}}} = 28.3$ mV/dec and an average swing SS $_{{\textsf {avg}}} = 59.8$ mV/dec over seven orders of drain current are achieved. In addition, complementary TFET inverters show good noise margins of $\textsf {NM}_{H} = 65$ mV (38.5 % $V_{{\textsf {DD}}}$ ) and NM $_{L} = 77$ mV (32.5 % $V_{{\textsf {DD}}}$ ) and also a high voltage gain even at $V_{{\textsf {DD}}} = 0.2$ V.

This letter presents an experimental capacitance–voltage ${C}$ – ${V}$ analysis for Si p-tunnel FETs (TFETs) fabricated on ultrathin body at various frequencies and temperatures. The capacitance distribution in TFETs is quite different compared with MOSFETs, due to different inversion charges partitioning between source and drain. Contrary to predictions from simulations, we provide experimental evidence for the first time that the contribution of the gate-to-source capacitance ${C}_{\textsf {gs}}$ to the total gate capacitance is much larger than expected, and even comparable to the gate-to-drain capacitance ${C}_{\textsf {gd}}$ at higher ${V}_{\textsf {ds}}$ and ${V}_{g}$ . Comparable values of ${C}_{\textsf {gs}}$ and ${C}_{\textsf {gd}}$ would imply that the Miller capacitance effect in TFETs-based circuits is less pronounced as predicted in simulations.

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both ${I}$ – ${V}$ and ${G}$ – ${V}$ characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: ${g}_{m}/{I}_{\text {d}}$ , ${g}_{m}/{g}_{ds}$ , ${f}_{T}$ and ${f}_{T}/{I}_{d}{V}_{d}$ , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to $40~\text {V}^{-1}$ , for currents lower than 10 nA/ $\mu \text{m}$ ; and 3) higher unity gain frequency per unit power for currents below 10 nA/ $\mu \text{m}$ .

We demonstrate for the first time, vertical Ge 0.92 Sn 0.08 /Ge and Ge gate-all-around (GAA) nanowire (NW) pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge NWs with 20 nm diameter and smooth sidewalls were achieved with optimized ICP-RIE and digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge NW pFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high I ON /I OFF ratio of 3×106. Further performance improvements, like ION, DIBL were achieved by adopting GeSn as the source. At V GS -V TH = -0.5V, ~32% ION enhancement for vertical heterojunction Ge092Sn008/Ge NW pFET is obtained compared with Ge control device. This is attributed to a smaller NiGeSn/GeSn contact resistivity and the existence of a valence band offset ΔE V at the Ge 0.92 Sn 0.08 /Ge heterojunction.

Vertical heterojunction Ge 0.92 Sn 0.08 /Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top-down approach are reported. With optimized processes, pFETs with nanowire diameters as small as 40 nm were achieved and a decent I ON /I oFF ratio of ~4×104 was obtained due to the GAA nanowire geometry and the GeSn/Ge heterostructure. Devices with larger nanowire diameters exhibited higher I ON , I ON /I OFF ratio and transconductance. Similar subthreshold swing (SS) characteristics were present in pFETs with various nanowire diameters considering the compensating effect between top source resistance and gate electrostatics induced by nanowire diameter.

We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing of such planar TFETs reaches 75 mV/decade over four orders of magnitude of drain current. Emphasis is placed on the capacitance–voltage analysis of TFETs. In contrast to simulation predictions, we provide experimental evidence that the contribution of $C_{\mathrm {gs}}$ to the total gate capacitance increases at on-state, which in turn results in a decrease of the gate-to-drain capacitance $C_{\mathrm {gd}}$ . This beneficial effect could result in a reduction of the Miller capacitance effect in TFETs-based circuits.