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We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuits that supports the involution delay model (Függer et al. 2019). Unlike the pure and inertial delay models typically used in digital timing analysis tools, the involution model faithfully captures short pulse propagation and related effects. Our Involution Tool facilitates experimental accuracy evaluation of variants of involution models, by comparing their timing and power predictions to those from SPICE and standard timing analysis tools. The tool is easily customizable w.r.t. instances of the involution model and circuits, and supports automatic test case generation and parameter sweeping. We demonstrate the capabilities of the Involution Tool by providing timing and power analysis results for three different circuits, namely, an inverter tree, the clock tree of an open-source processor, and a combinational circuit that involves multi-input NAND gates. Our evaluation uses two different technologies (15 nm and 65 nm CMOS), and three different variants of involution channels (Exp, Hill and SumExp-channels). It turns out that the timing and power predictions of all involution models are significantly better than the predictions obtained by standard digital simulations for the inverter tree and the clock tree, with the SumExp-channel channel clearly outperforming the others. For the NAND circuit, the performance of any involution model is generally comparable but not significantly better than that of standard models, however, which reveals some shortcomings of the existing involution channels for modeling multi-input gates. • Presentation of the Involution Tool for digital timing and power simulation • Fully automatic execution of elaborate dynamic delay estimation models • Accuracy comparison of timing predictions of different delay models • Experimental validation of different switching waveforms • Evidence for shortcomings of single-input single-output involution channels [ABSTRACT FROM AUTHOR]

Abstract: In this paper, the effect of vacuum pressures on the performance of a velvet cathode under repetitive high-current pulse discharges was experimentally investigated. A series of tests were carried out on a vacuum diode, powered by a ˜300 kV, ˜5 ns, ˜100 Ω and 1–300 Hz pulse generator. Typical results of discharge waveforms, vacuum pressure rises, and SEM pictures for total 1000 shots are presented and head-to-head compared at 30 Hz, 100 Hz, and 300 Hz, respectively. With the pulse repetition rate (rep-rate) increasing, it was found that the equilibrium pressure during the pulse series from 30 Hz to 300 Hz increased hyper-linearly that led to diode pressures of ˜0.01 Pa–˜1 Pa. When the pressure exceeded 0.1 Pa, the beam current degradation was observed in terms of pulse-to-pulse instability increment and pulse width decline. Velvet curling and erosion also became apparent. The nature behind these results was discussed closely related to the gas ionization due to such high background pressures. Technical methods to improve the vacuum condition for a repetitive operated velvet cathode were also proposed. [ABSTRACT FROM AUTHOR]

Nonlinear effects are one of the main causes of pulse degradation in high bit-rate transmission systems and several architectures have been proposed to compensate them by means of optical phase conjugation. In this letter, a new method to exploit an optical phase conjugator for nonlinearity cancellation is disclosed. The proposed method is simpler than those previously described in literature and allows a relevant improvement of systems performances. Link-design rules are analytically studied; moreover, their effectiveness is numerically demonstrated for different applications. This technique can apply to any bit rates and modulation formats. [ABSTRACT FROM PUBLISHER]