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3. HCIP: Hybrid Short Long History Table-based Cache Instruction Prefetcher.

5. Advertising LED System Using PIC18F4550 Microcontroller and LED Lighting

6. An Observational Approach to Defining Linearizability on Weak Memory Models

7. What Makes Petri Nets Harder to Verify: Stack or Data?

13. Secure Computation of MIPS Machine Code

14. Toward an Energy Efficient Language and Compiler for (Partially) Reversible Algorithms

15. AUSPICE: Automatic Safety Property Verification for Unmodified Executables

16. A General Lattice Model for Merging Symbolic Execution Branches

17. Refactoring Preserves Security

20. Disseny d'un microprocessador en una FPGA basat en màquines algorítmiques

21. A Tamper and Leakage Resilient von Neumann Architecture

22. Modular Deductive Verification of Multiprocessor Hardware Designs

27. A Basic Sequential MIPS Machine

28. Microcode Verification – Another Piece of the Microprocessor Verification Puzzle

29. Mechanized, Compositional Verification of Low-Level Code

30. Embedded Peripherals

32. Program Flow Instructions

34. Guard-Based Partial-Order Reduction

35. Improved State Space Reductions for LTL Model Checking of C and C++ Programs

36. Membrane Systems and Hypercomputation

37. A Fully Homomorphic Crypto-Processor Design : Correctness of a Secret Computer

38. Proof Pearl: A Verified Bignum Implementation in x86-64 Machine Code

40. UTLEON3 Implementation Details

42. Selection in the Presence of Memory Faults, with Applications to In-place Resilient Sorting

43. A Functional View of Imperative Information Flow

44. A Sound Reduction of Persistent-Sets for Deadlock Detection in MPI Applications

45. Juggrnaut – An Abstract JVM

46. A Reversible Processor Architecture and Its Reversible Logic Design

47. On-the-Fly Inlining of Dynamic Dependency Monitors for Secure Information Flow

48. On the Correctness of the SIMT Execution Model of GPUs

49. Lazy Abstraction with Interpolants for Arrays

50. Advances in the TAU Performance System

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