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1,045 results on '"Processor array"'

1. Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices

Author

Atef Ibrahim and Fayez Gebali

Subjects
Finite field multiplication, IoT security, Cryptography, IoT-edge devices, Parallel processing, Processor array, Engineering (General). Civil engineering (General), TA1-2040
Abstract

Adoption of IoT technology without considering its security implications may expose network systems to a variety of security breaches. In network systems, IoT edge devices are a major source of security risks. Implementing cryptographic algorithms on most IoT edge devices can be difficult due to their limited resources. As a result, compact implementations of these algorithms on these devices are required. Because the field multiplication operation is at the heart of most cryptographic algorithms, its implementation will have a significant impact on the entire cryptographic algorithm implementation. As a result, in this paper, we propose a small hardware accelerator for performing field multiplication on edge devices. The hardware accelerator is primarily composed of a processor array with a regular structure and local interconnection among its processing elements. The main advantage of the proposed hardware structure is the ability to manage its area, delay, and consumed energy by choosing the appropriate word size l. We implemented the proposed structure using ASIC technology and the obtained results attain average savings in the area of 95.9%. Also, we obtained significant average savings in energy of 63.2%. The acquired results reveal that the offered hardware accelerator is appropriate for usage in resource-constrained IoT edge devices.

Published
2022
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2. Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices.

Author

Ibrahim, Atef and Gebali, Fayez

Subjects
ARRAY processors, INTERNET of things, HARDWARE, FINITE fields, MULTIPLICATION
Abstract

Adoption of IoT technology without considering its security implications may expose network systems to a variety of security breaches. In network systems, IoT edge devices are a major source of security risks. Implementing cryptographic algorithms on most IoT edge devices can be difficult due to their limited resources. As a result, compact implementations of these algorithms on these devices are required. Because the field multiplication operation is at the heart of most cryptographic algorithms, its implementation will have a significant impact on the entire cryptographic algorithm implementation. As a result, in this paper, we propose a small hardware accelerator for performing field multiplication on edge devices. The hardware accelerator is primarily composed of a processor array with a regular structure and local interconnection among its processing elements. The main advantage of the proposed hardware structure is the ability to manage its area, delay, and consumed energy by choosing the appropriate word size l. We implemented the proposed structure using ASIC technology and the obtained results attain average savings in the area of 95.9%. Also, we obtained significant average savings in energy of 63.2%. The acquired results reveal that the offered hardware accelerator is appropriate for usage in resource-constrained IoT edge devices. [ABSTRACT FROM AUTHOR]

Published
2022
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3. JPEG Encoding on Fine-Grain Manycore Platforms

Author

Abbott, Thomas Walker

Subjects
Computer engineering, Electrical engineering, JPEG encoding, many-core, processor array
Abstract

JPEG encoding is a powerful image compression algorithm capable of compressingimage data at the cost of image quality. A variety of architectures implement JPEG encoding,each leveraging either serial execution superiority (general-purpose programmable processors),massive parallelization abilities (GPUs), or dynamic architecture arrangements (FPGAs).However, all these architectures need help to simultaneously handle the serial and parallelcomponents of the JPEG encoding algorithm. This thesis proposes 29 JPEG encoderimplementations on the KiloCore platform (a fine-grain manycore processor array), compareseach algorithm to one another, and compares the top algorithms to designs on differingarchitectures.This work benchmarks throughput, throughput per area, energy per megapixel encoded,and energy-delay product across 29 KiloCore JPEG encoder versions. Furthermore, this workcompares the top KiloCore designs against JPEG implementations on a Xilinx Zynq-7000 FPGA(VISENGI), TI C66x Embedded Processor, Intel i9 9900 CPU (libjpeg-turbo), and IntelPlatinum 8168 with an Nvidia A100 GPU (nvJPEG).JPEG encoding implementations on KiloCore require low amounts of energy while stillreaching competitive throughput. JPEG encoding implementations on KiloCore achieve higherthroughput than the C66x and Intel i9 9900 JPEG encoders by at least 6.6×. JPEG encodingimplementations on KiloCore have the lowest area usage and have the highest throughput perarea by 1.45× to 100×. JPEG encoding implementations on KiloCore have the lowest energy permegapixel encoded of tested general-purpose processors, by 1.88× to 100×. Finally, JPEGencoding implementations on KiloCore boast a 20× to 261,733× lower energy-delay product than its general-purpose industry competition.

Published
2023

4. A mathematical programming method for constructing the shortest interconnection VLSI arrays.

Author

Ding, Hao, Qian, Junyan, Zhao, Lingzhong, and Zhai, Zhongyi

Subjects
*ARRAY processors, *VERY large scale circuit integration, *INTEGER programming, *PARALLEL processing, *MATHEMATICAL programming
Abstract

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound. • A mathematical model for VLSI array reconstruction is established. • The interconnection of the array is set to a function with a fixed integer variable. • The problem is transformed into solving the objective function. • A novel method was proposed constructing tightly coupled sub-arrays. [ABSTRACT FROM AUTHOR]

Published
2021
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5. Design and implementation of massively parallel fine-grained processor arrays

Author

Walsh, Declan and Dudek, Piotr

Subjects
621.3, SIMD, MIMD, Parallel Processing, Multi-core, ASIC, Processor Array, FPGA
Abstract

This thesis investigates the use of massively parallel fine-grained processor arrays to increase computational performance. As processors move towards multi-core processing, more energy-efficient processors can be designed by increasing the number of processor cores on a single chip rather than increasing the clock frequency of a single processor. This can be done by making processor cores less complex, but increasing the number of processor cores on a chip. Using this philosophy, a processor core can be reduced in complexity, area, and speed to form a very small processor which can still perform basic arithmetic operations. Due to the small area occupation this can be multiplied and scaled to form a large scale parallel processor array to offer a significant performance. Following this design methodology, two fine-grained parallel processor arrays are designed which aim to achieve a small area occupation with each individual processor so that a larger array can be implemented over a given area. To demonstrate scalability and performance, SIMD parallel processor array is designed for implementation on an FPGA where each processor can be implemented using four ‘slices’ of a Xilinx FPGA. With such small area utilization, a large fine-grained processor can be implemented on these FPGAs. A 32 × 32 processor array is implemented and fast processing demonstrated using image processing tasks. An event-driven MIMD parallel processor array is also designed which occupies a small amount of area and can be scaled up to form much larger arrays. The event-driven approach allows the processor to enter an idle mode when no events are occurring local to the processor, reducing power consumption. The processor can switch to operational mode when events are detected. The processor core is designed with a multi-bit data path and ALU and contains its own instruction memory making the array a multi-core processor array. With area occupation of primary concern, the processor is relatively simple and connects with its four nearest direct neighbours. A small 8 × 8 prototype chip is implemented in a 65 nm CMOS technology process which can operate at a clock frequency of 80 MHz and offer a peak performance of 5.12 GOPS which can be scaled up to larger arrays. An application of the event-driven processor array is demonstrated using a simulation model of the processor. An event-driven algorithm is demonstrated to perform distributed control of distributed manipulator simulator by separating objects based on their physical properties.

Published
2015

6. Scalable energy-efficient parallel sorting on a fine-grained many-core processor array.

Author

Stillmaker, Aaron, Bohnenstiehl, Brent, Stillmaker, Lucas, and Baas, Bevan

Subjects
*ARRAY processors, *INTEL microprocessors, *ARRAY processing, *MULTICORE processors, *C++, *PARALLEL processing, *DATABASES
Abstract

Three parallel sorting applications and two list output protocols for the first phase of an external sort execute on a fine-grained many-core processor array that contains no algorithm-specific hardware acting as a co-processor with a variety of array sizes. Results are generated using a cycle-accurate model based on measured data from a fabricated many-core chip, and simulated for different processor array sizes. The data shows most energy efficient first-phase many-core sort requires over 65 × lower energy than GNU C++ standard library sort performed on an Intel laptop-class processor and over 105 × lower energy than a radix sort running on an Nvidia GPU. In addition, the highest first-phase throughput many-core sort is over 9.8 × faster than the std::sort and over 14 × faster than the radix sort. Both phases of a 10 GB external sort require 6.2 × lower energy × time energy delay product than the std::sort and over 13 × lower energy × time than the radix sort. • Many-core processors can serve as a high-performance energy-efficient co-processor. • A massive array of simple processors can efficiently perform large modular sorts. • These sorts easily scale with different sized general purpose processing arrays. • A first-phase many-core sort requires 105x less energy than a radix sort on a GPU. • A 10 GB many-core external sort requires 6.2x lower EDP than std::sort on a laptop. [ABSTRACT FROM AUTHOR]

Published
2020
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12. A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting

Author

Junyan Qian, Yiping Wang, Liang Chang, Zhide Zhou, and Lingzhong Zhao

Subjects
Integer programming, fault tolerance, reconfiguration, processor array, algorithm, Electrical engineering. Electronics. Nuclear engineering, TK1-9971
Abstract

Increasing the size of target arrays is beneficial to reuse fault-free processing elements (PEs) for reconfiguring 2-D mesh-connected processor arrays with faults. In this paper, we discuss the reconfiguration problem under the row and column rerouting constraint. We present a novel approach, making use of the idea of integer programming, for constructing larger size target arrays. Meanwhile, we propose a new method to deal with the fault-free processing elements in the physical row that is selected for exclusion. Compared with the state-of-arts algorithms, our method can make the fault-free PEs used as much as possible, which means the size of the target array can be significantly improved. Experimental results show that, compared with previous studies, the proposed algorithm achieves better results in terms of the usage rate of fault-free PEs in the host array.

Published
2017
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15. A high-performance VLSI array reconfiguration scheme based on network flow under row and column rerouting

Author

Zhongyi Zhai, Hao Ding, Lingzhong Zhao, and Junyan Qian

Subjects
Very-large-scale integration, Interconnection, Computer Networks and Communications, Computer science, business.industry, Reliability (computer networking), Control reconfiguration, Flow network, Processor array, Bottleneck, Theoretical Computer Science, Artificial Intelligence, Hardware and Architecture, Minimum cut, business, Software, Computer hardware
Abstract

The reconfiguration algorithms have been extensively investigated to ensure the reliability and stability for the processor arrays with faults. It is important to reduce the power consumption, capacitance and communication costs in the processors by reducing the interconnection length of the VLSI array. This paper discusses the reconfiguration problem of the high-performance VLSI processor array under the row and column rerouting constraints. A novel method, making use the idea of network flow, is proposed in this paper. Firstly, a network flow model of the VLSI processor array is constructed, such that the high-performance VLSI target array can be obtained by utilizing the minimal cost flow algorithm. Secondly, we propose a new strategy for bottleneck row selection in the logical array using the minimum cut technique, which can find a more suitable bottleneck row. Finally, we conducted reliable experiments to clearly reveal the efficiency of the new rerouting scheme and algorithm in reducing the number of long interconnects. The experimental results show that, for a host array with size of 256×256, the number of long interconnects in the subarray can be reduced by up to 79.22% and 55.88% without performance penalty for random faults with density of 1% and 25% respectively, when compared with state-of-the-art. In addition, the proposed scheme improves existing algorithm in terms of subarray size. On a 256×256 host array with 25% faulty density, the average improvement in subarray size is up to 3.77% compared with state-of-the-art.

Published
2021
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16. A mathematical programming method for constructing the shortest interconnection VLSI arrays

Author

Junyan Qian, Hao Ding, Zhongyi Zhai, and Lingzhong Zhao

Subjects
Very-large-scale integration, Interconnection, Hardware and Architecture, Computer science, Control reconfiguration, Fault tolerance, Parallel computing, Electrical and Electronic Engineering, Solver, Processor array, Integer programming, Software, Integer (computer science)
Abstract

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound.

Published
2021
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18. VISCUBE: A Multi-Layer Vision Chip

Author

Zarándy, Ákos, Rekeczky, Csaba, Földesy, Péter, Carmona-Galán, Ricardo, Cembrano, Gustavo Liñán, Gergely, Soós, Rodríguez-Vázquez, Ángel, Roska, Tamás, and Zarándy, Ákos, editor

Published
2011
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19. Removing an Object from Video Sequence Algorithm Implemented on Analog CNN and DSP Microprocessors

Author

ARSLAN, Emel, ARIK, Sabri, Hutchison, David, Kanade, Takeo, Kittler, Josef, Kleinberg, Jon M., Mattern, Friedemann, Mitchell, John C., Naor, Moni, Nierstrasz, Oscar, Pandu Rangan, C., Steffen, Bernhard, Sudan, Madhu, Terzopoulos, Demetri, Tygar, Doug, Vardi, Moshe Y., Weikum, Gerhard, Diamantaras, Konstantinos, editor, Duch, Wlodek, editor, and Iliadis, Lazaros S., editor

Published
2010
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22. Parallelization Approaches for Hardware Accelerators – Loop Unrolling Versus Loop Partitioning

Author

Hannig, Frank, Dutta, Hritam, Teich, Jürgen, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Berekovic, Mladen, editor, Müller-Schloer, Christian, editor, Hochberger, Christian, editor, and Wong, Stephan, editor

Published
2009
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23. Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Author

Kissler, Dmitrij, Strawetz, Andreas, Hannig, Frank, Teich, Jürgen, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Svensson, Lars, editor, and Monteiro, José, editor

Published
2009
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25. PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications

Author

Hannig, Frank, Ruckdeschel, Holger, Dutta, Hritam, Teich, Jürgen, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Woods, Roger, editor, Compton, Katherine, editor, Bouganis, Christos, editor, and Diniz, Pedro C., editor

Published
2008
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26. Modeling of Interconnection Networks in Massively Parallel Processor Architectures

Author

Kupriyanov, Alexey, Hannig, Frank, Kissler, Dmitrij, Teich, Jürgen, Lallet, Julien, Sentieys, Olivier, Pillement, Sébastien, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Rangan, C. Pandu, editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Lukowicz, Paul, editor, Thiele, Lothar, editor, and Tröster, Gerhard, editor

Published
2007
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27. The ZEN Experiment Specification Language

Author

Prodan, Radu, Fahringer, Thomas, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Rangan, C. Pandu, editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Prodan, Radu, and Fahringer, Thomas

Published
2007
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28. Accelerating the Viterbi Algorithm for Profile Hidden Markov Models Using Reconfigurable Hardware

Author

Oliver, Timothy F., Schmidt, Bertil, Jakop, Yanto, Maskell, Douglas L., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Alexandrov, Vassil N., editor, van Albada, Geert Dick, editor, Sloot, Peter M. A., editor, and Dongarra, Jack, editor

Published
2006
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29. Controller Synthesis for Mapping Partitioned Programs on Array Architectures

Author

Dutta, Hritam, Hannig, Frank, Teich, Jürgen, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Dough, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Grass, Werner, editor, Sick, Bernhard, editor, and Waldschmidt, Klaus, editor

Published
2006
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30. Biological Sequence Analysis with Hidden Markov Models on an FPGA

Author

Yanto, Jacop, Oliver, Timothy F., Schmidt, Bertil, Maskell, Douglas L., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Srikanthan, Thambipillai, editor, Xue, Jingling, editor, and Chang, Chip-Hong, editor

Published
2005
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31. Computing Transitive Closure Problem on Linear Systolic Array

Author

Milovanović, I. Ž., Milovanović, E. I., Randjelović, B. M., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Li, Zhilin, editor, Vulkov, Lubin, editor, and Waśniewski, Jerzy, editor

Published
2005
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32. Automatic FIR Filter Generation for FPGAs

Author

Ruckdeschel, Holger, Dutta, Hritam, Hannig, Frank, Teich, Jürgen, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Hämäläinen, Timo D., editor, Pimentel, Andy D., editor, Takala, Jarmo, editor, and Vassiliadis, Stamatis, editor

Published
2005
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33. Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array

Author

Yamada, Yutaka, Amano, Hideharu, Koibuchi, Michihiro, Jouraku, Akiya, Anjo, Kenichiro, Nishimura, Katsunobu, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Yang, Laurence T., editor, Guo, Minyi, editor, Gao, Guang R., editor, and Jha, Niraj K., editor

Published
2004
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34. Configurable Microprocessor Array for DSP Applications

Author

Maslennikow, Oleg, Shevtshenko, Juri, Sergyienko, Anatoli, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Wyrzykowski, Roman, editor, Dongarra, Jack, editor, Paprzycki, Marcin, editor, and Waśniewski, Jerzy, editor

Published
2004
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36. Agile reactive navigation for a non‐holonomic mobile robot using a pixel processor array

Author

Walterio W. Mayol-Cuevas, Rui Fan, Stephen J. Carey, Piotr Dudek, Colin Greatwood, Laurie Bose, Thomas Richardson, Yanan Liu, and Jianing Chen

Subjects
FOS: Computer and information sciences, Computer science, Machine vision, Computer Vision and Pattern Recognition (cs.CV), Computer Science - Computer Vision and Pattern Recognition, Image processing, 02 engineering and technology, Processor array, Bottleneck, Computer Science - Robotics, QA76.75-76.765, Robustness (computer science), Photography, 0202 electrical engineering, electronic engineering, information engineering, Computer vision, Computer software, Electrical and Electronic Engineering, TR1-1050, Pixel, business.industry, 020206 networking & telecommunications, Mobile robot, Image plane, Signal Processing, 020201 artificial intelligence & image processing, Computer Vision and Pattern Recognition, Artificial intelligence, business, Robotics (cs.RO), Software
Abstract

This paper presents an agile reactive navigation strategy for driving a non-holonomic ground vehicle around a preset course of gates in a cluttered environment using a low-cost processor array sensor. This enables machine vision tasks to be performed directly upon the sensor's image plane, rather than using a separate general-purpose computer. We demonstrate a small ground vehicle running through or avoiding multiple gates at high speed using minimal computational resources. To achieve this, target tracking algorithms are developed for the Pixel Processing Array and captured images are then processed directly on the vision sensor acquiring target information for controlling the ground vehicle. The algorithm can run at up to 2000 fps outdoors and 200fps at indoor illumination levels. Conducting image processing at the sensor level avoids the bottleneck of image transfer encountered in conventional sensors. The real-time performance of on-board image processing and robustness is validated through experiments. Experimental results demonstrate that the algorithm's ability to enable a ground vehicle to navigate at an average speed of 2.20 m/s for passing through multiple gates and 3.88 m/s for a 'slalom' task in an environment featuring significant visual clutter., Comment: 7 pages

Published
2021
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39. Implementation of Givens QR-Decomposition in FPGA

Author

Sergyienko, Anatoli, Maslennikov, Oleg, Goos, Gerhard, editor, Hartmanis, Juris, editor, van Leeuwen, Jan, editor, Wyrzykowski, Roman, editor, Dongarra, Jack, editor, Paprzycki, Marcin, editor, and Waśniewski, Jerzy, editor

Published
2002
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41. The Dutch Team

Author

Jonker, Pieter, van Geest, Will, Groen, Frans, Stone, Peter, editor, Balch, Tucker, editor, and Kraetzschmar, Gerhard, editor

Published
2001
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