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Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.

We find a fundamental limit of channel-length scaling for Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) FETs. We optimize a set of devices with different channel lengths, from 10 nm to 100 nm, through an optimization algorithm to meet a pre-determined criterion for drain-to-source subthreshold leakage-current and breakdown voltage. We identify an optimum channel length of 40 nm for both 5V and 3.3V planar LDMOS devices. To assess the possible importance of source-to-drain tunneling in short-channel LDMOS devices, we also perform a quantum mechanical study of 5 nm to 15 nm channel length LDMOS devices. We find that classical effects, rather than quantum tunneling, determine the scaling limit of LDMOS.

In conventional theoretical methods for studying dissipative quantum transport, numerical complexity forces us to ignore important nonlocal effects, or to restrict attention to very small or one-dimensional systems. The authors present an efficient method, based on the Pauli master equation, that treats dissipative quantum transport while explicitly taking into account the nonlocal and inelastic nature of the scattering processes. Applying the method to a realistic semiconductor device reveals that, even at the nanoscale, electronic transport is predominantly dissipative, and demonstrates quantitatively that scattering due to interface roughness has a drastic impact on device performance.

We present a theoretical study - based on the effective-mass approximation - of scattering of electrons with microscopic roughness at the oxide-semiconductor interface for ultra-thin body (UTB) double gate (DG) and silicon-on-insulator (SOI) MOSFETs. Discrete edge roughness is introduced along the oxide-semiconductor interface by locally adding or removing 1–2 Silicon atomic layers. The random nature of the interface roughness is characterized by an exponential autocovariance. The dissipative impact of surface roughness scattering is obtained by averaging over a sample space of devices with identical structure but with different random interface-roughness patterns. Our results show significant variations in the ON current among the ‘roughened’ samples along with the introduction and impact of quantum confinement effects caused by interface roughness. Finally, we report the dependence of these results on the semiconductor/channel thickness.

Quantum simulation of electronic transport in double gate (DG) field-effect transistors (FETs) and FinFETs is usually deemed to be required as the devices are scaled to the nanometer length-scale. Here, we present results obtained using a simulation program to model ballistic quantum transport in these devices. Our quantum simulations show the presence of quasi bound electronic states in the channel and Fano-interference phenomenon in the transport behavior of ultra-thin body (UTB) Si DG MOSFETs. Vortices in electron wavefunctions are also reported at energies at which transmission zeros (antiresonance) occur.