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The phase-locked loop is a technique that has contributed significantly to technological advancements in many applications in the fast-evolving digital era. In this paper, a Phase Locked Loop (PLL) is designed using 90 nm CMOS technology node with 1.8 V supply voltage. It features a PLL design with minimum power consumption of 194.26 µW with better transient analysis and DC analysis in an analog-to-digital environment. The proposed PLL design provides the best solution for many applications where a PLL is required with high performance but has to be accommodated in less area and low power consumption than state-of-the-art methods. This PLL not only works at high speed but also makes whole system work at low power in a very effective manner, which suits the present digital electronics circuits. [ABSTRACT FROM AUTHOR]

Multiple-input, multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems with multiple input antennas and multiple output antennas in dynamic environments face the challenge of channel estimation. To overcome this challenge and to improve the performance and signal-tonoise ratio, in this paper we used the Kalman filter for the correct estimation of the signal in dynamic environments. To obtain the original signal at the receiver end bit error rate factor plays a major role. If the signal to noise ratio is high and the bit error rate is low then signal strength is high, the signal received at the receiver end is almost similar to the ith transmitted signal. The dynamic tracking characteristic of Kalman filter is used to establish a dynamic space-time codeword and a collection of orthogonal pilot sequences to prevent interference among transmissions in this paper. Using the simulation, the Kalman filter method can be compared to the other channel estimation method presented in this paper that can track timevarying channels rapidly. [ABSTRACT FROM AUTHOR]