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CMOS integrated circuits consisting of MOSFETs have tradeoffs among their performance parameters. Hence they need minimization in those tradeoffs calling for multi objective optimization to yield a circuit with enhanced characteristics. To perform simultaneous optimization of the Phase locked loop (PLL) performances using an effective multi objective optimization technique saving the designer’s time and causing the near best performance is the motivation of this work. Though the designer can optimize the circuit in the netlist level, it is less effective and a time consuming iterative process and sometimes it is next to impossible for complex and nanoscale circuits with large number of MOSFET devices and interconnects. Performance parameters like phase noise, lock time and power consumption are optimized subject to the practical design constraints using an efficient multi-objective optimization technique, infeasibility driven evolutionary algorithm (IDEA) in a real time environment. Using design parameters like the channel length and width of the MOSFETs for optimal performance, the PLL is simulated for model validation. Significantly superior performance achieved by the designed PLL is demonstrated. The phase noise, average power consumption and lock time achieved here are −126.3 dBc/Hz at 1 MHz offset frequency, 1.523 mW and 50 nS respectively.

In this paper, the performance of FinFET has been examined by changing the fin width which affects the device performance. The fin width has been changed by keeping the device width fixed and varying the width of the oxide layer by electrical characterization and simulation. The device width is fixed at 50nm and the oxide layer width is varied from 10nm to 3nm. Here five different parameters such as drain current (ID), transconductance (g m ), cutoff frequency (f T ), gain bandwidth product (GBW), and power (P) are computed to study the effect of oxide layer width of the device. It has been observed from the simulation that at lower oxide layer width ID and g m show maximum value, and at medium value of oxide layer width f T and GBW give better performance. The power consumption of FinFET is lesser when the oxide layer width reduces.

The read instability of conventional 6T-SRAM cell has made the 8T-SRAM cell a substitute for high data reliability. But the single ended nature of read operation demands a complete Vdd swing of high capacitive read bit lines leading to large energy consumption. A novel assist technique using charge recycling concept is proposed here which reduces the read and write energy by reducing the voltage swing. Mathematical analysis of the proposed technique, theoretically predicts the read and write energy to reduce by 75% and 25% respectively compare to that of the conventional 8T-SRAM array. Experimental simulation using predictive technology model demonstrates these two energy consumptions to be reduced by 58% and 27% respectively. The proposed technique also reduces the leakage current flow in the standby cells and hence the energy consumption. The dummy read current flow in the half-selected cells is also controlled significantly in the proposed technique. The stability of the SRAM cell remains unchanged by the insertion of the proposed assist technique.

In modern SOC design SRAM has become an integral part owing to its capability to form a bridge and overcome the speed mismatch problem between the high speed processor and the low speed data storage devices. Because of the read and write operation of SRAM cell having conflicting transistor sizing requirement, it is very difficult to maintain the transistor size to satisfy both the needs. The destructive nature of read operation enforces a serious thought about SRAM cell data stability. Transistor sizing and cell stability already being a critical problem becomes even more critical when we consider the process and temperature variation. Thus the SRAM should be designed with keeping the process and temperature variation in mind. The random fluctuation in device parameters such as transistor width, length, oxide thickness, oxide capacitance and doping concentration leads to variation in the threshold voltage and other transistor characteristics. The change in these transistor characteristics alters the SRAM cell performance. Hence this should also be taken care of to ensure the cell performance to be in the desired range even in presence of random fluctuation during fabrication process. The various performance measure such as SNM, write SNM, speed and power consumption must be tested under worst process corner as well over a wide temperature range to ensure that they lie in the acceptable range during worst operating condition. Also these parameters must be tested using Monte Carlo simulation to ensure a robust operation in presence of random fluctuation during fabrication process.

The modern electronics gadget has influenced tremendously every aspects of life. The demand to add more and more functionality has forced to increase the performance of the processor. To ensure a robust data supply to the processor a high performance, stable and low power SRAM is also of utmost necessity. An indirect read SRAM cell is proposed here which eliminates the read noise insertion to increase the data stability. It also consumes 41% less energy compared to the conventional SRAM cell. The SRAM cell is designed to be written single ended using only one write access transistor. The cell reduces the energy consumption by reducing the short circuit current and also reducing the number of leakage path. The cell also has a high write speed since the storage data node is a floating node and not connected to the ground.

Power theft is normally done by two methods that is bypassing or hooking. So to detect it, a system (current measuring and comparing) is proposed in which the household distribution of current is done indirectly from the electric pole to an intermediate distributor box and then to the individual houses. The current is measured periodically in the distributor box and is posted to the server database for each house using GSM/GPRS module. Similarly, for each house electric meter is designed which can measure the value of the current and post the same to the server database periodically using GSM/GPRS module. At the time of the installation of the electric meter the details of the users are stored in the database through a user friendly mobile application including the address, latitude, longitude using mobile GPS and the photograph of the user's house/area. Upon successful comparison between the current values from distributor box and electric meter in the server if we get a marginal difference between the currents then the theft is detected. Finally, the details of the user are shared with the authorized mobile application including the address and photograph of the area. The latitude and longitude are also used to show the area of theft in Google maps. And hence the required steps are taken. The same process is used for hooking but on the individual electric poles.

This paper reviews the design of phase locked loop (PLL) using recently reported charge pump circuits. Lock time, phase noise, lock range and reference spur of each charge pump circuit are investigated. Though improved charge pump circuits are designed recently, their performance is not as effective as the basic charge pump PLL (CP-PLL). Initially the design of PLL using the basic charge pump is completed in this paper and then the PLL using improved charge pumps are redesigned in CMOS 180 nm technology and simulated using Cadence Virtuoso Analog Design Environment. Finally all the charge pumps are compared with respect to the PLL performances. The current starved voltage controlled oscillator (VCO) used for the design of PLL brings about a tuning range of 119.5 MHz to 2.3 GHz. The PLL using different charge pumps produces a lock time which varies from 204 ns to 329 ns. The other parameters like lock range, phase noise and reference spur are also examined.

Read noise insertion problem of conventional read method of 6T-SRAM cell has forced to think about indirect read. Indirect read though eliminates read noise insertion but also take away the capability to use differential sensing thus leading to more energy and time consumption. Charge recycling concept must be followed by the SRAM cell to reduce energy consumption. An indirect read technique based SRAM is proposed which is capable to follow differential sensing along with following charge recycling technique. Thus it makes the proposed SRAM cell high stable, fast and low energy consuming. Theoretical estimation states that write and read energy consumption of the proposed cell is 12.5% and 25% smaller than those of the compared RDFD-SRAM. Stability analysis shows that the read SNM of the proposed cell which is the most critical stability index is same as its retention SNM and is 317% of the read SNM of conventional 6T-SRAM. The delay analysis also states the fastness of proposed cell.

In this paper, the quality of service (QoS) of massive MIMO wireless system with time division duplexing (TDD) protocol has been evaluated. Though employment of hundreds of antenna elements at base station (BS) promises many fold enhancement of degrees of freedom in the system, the complexity in channel estimation has also increased in same proportion. The spectrum overhead in massive MIMO system with conventional frequency division duplexing (FDD) is unmanageably high as it estimates both links separately. TDD protocol, though it is not popular in legacy wireless systems, may be best choice for massive MIMO as it reduces the spectrum overhead significantly by exploiting the reciprocity between channels for both the links. The QoS parameters like average sum-rate and outage probability are considered in this paper for performance evaluation of massive MIMO with TDD protocol has been evaluated in terms of system bit error rate and average sum-rate.

In a system though the analog circuits occupy very less space but they require far more design time than the digital circuits. This is due to the fact that the number of performance measures of an analog circuit is more than those for digital circuits. Predicting and improving the performance, robustness and overall cost of such systems is a major concern in the process of automation. In the automation process, optimization of performances subjected to a verity of environmental constraints is a central task. In this chapter, efficient analog circuit sizing techniques and their optimization are surveyed.

The performance of nanoscale radio frequency integrated circuits (RFIC) is influenced by the circuit parasitics and device dimensions. The present work predicts the design parameters of CMOS ring oscillator (CMOS RO) for its optimal performance and designs the CMOS RO using these parameters in Cadence Virtuoso Analog Design Environment with GPDK 90 nm process. An efficient optimization technique, non-dominated sorting based genetic algorithm (NSGA-II) is used to minimize the power consumption and phase noise of the circuit at its schematic and physical levels. This optimization is also carried out by taking into account the extracted parasitics that would be present in the physical integrated circuit and by considering the variations in the process parameters. The optimization algorithm, effectively converts several time consuming design iterations to a single step design, ensuring the near best performance of the CMOS RO with all possible real time constraints. In this proposed design methodology the optimization objectives such as frequency, power and phase noise are formulated in such a manner that those are implicitly parasitic aware. The design of CMOS RO with different number of stages is verified by performing simulations for transient and noise analysis using Cadence tools.

This paper presents a novel design methodology for design of optimal and robust current starved voltage controlled oscillator (CSVCO) circuit. A recently developed multiobjective optimization technique infeasibility driven evolutionary algorithm is used to minimize the power and the phase noise of the circuit at its schematic and physical level. The multiobjective optimization is carried out by taking into account the extracted parasitics that would be present in the physical integrated circuit and the random variations of parameters during fabrication in foundry. This method helps the designer in semiconductor industry by effectively reducing several time consuming design iterations to a single iteration ensuring the near optimal performance of the CSVCO. The performance of the circuit is validated by carrying out simulations for transient and noise analysis in Cadence tools using 90 nm 1P9M CMOS process.

Dead zone very often poses to be a limitation in the high performance phase locked loops (PLLs). The design of a dead zone free PLL with fast locking and low phase noise capability is proposed. This is achieved by using a voltage variable delay element (VVDE) in the feedback path or reset path of the phase frequency detector (PFD). A feedback from one of the inputs of charge pump circuit is used to retain the overall PFD delay slightly positive to escape dead zone at lesser phase noise. The PLL performance with this proposed PFD is analysed in the cadence design environment. It attains phase noise of –110.5 dBc/Hz at 1 MHz offset frequency which is superior as compared to the other two reported techniques. Achieving this superior phase noise performance the PLL consumes lesser power of 2.56 mW at the cost of 5% extra physical area. This performance is also compared with that of PLL where no delay and fixed delay element is used to reduce the dead zone.

In this paper a popular multiobjective optimization Non-dominated Sorting Genetic Algorithm (NSGA-II) based integrated circuit design methodology using simple equation models is presented. The method is applied to CMOS ring oscillator circuit where the design parameters are estimated so that the circuit offers optimal performance. The circuit is designed using these parameters in Cadence Virtuoso Analog Design Environment (ADE) with GPDK 90nm process to test the predicted performance. The proposed method saves the design cycle time ensuring the optimal performance of the CMOS ring oscillator in a constrained environment.

Though CMOS logic inverter is widely appreciated because of its negligible static power consumption still sometimes it is deprecated because of the high dynamic power consumption. The high dynamic power consumption is because of the charging and discharging of the load capacitor and also because of the unwanted short-circuits current from Vdd to ground. The proposed three transistor saturated NMOS inverter reduces the short-circuit current and hence reduces the overall power consumption. The proposed inverter reduces the average power consumption by 35% for any input signal of frequency less than or equal to 1 MHz and by 15% for any input signal up to around 10MHz. But the power consumption slowly increases when the input frequency goes beyond 100 MHz. So the proposed inverter can be used in MHz applications to save a good amount of power.

CMODE (Combining Multi-objective Optimization with Differential Evolution) technique has been proved to be very efficient to design a low power low phase noise LC Voltage Controlled Oscillator (VCO). The proposed technique optimizes the power consumption and phase noise of the 3.3-4 GHz LC-VCO for GSM-900 standard. The performance indices are optimized by using CMODE technique in MATLAB and corresponding optimal design parameters are obtained and implemented in 90 nm CMOS technology. The Figure Of Merit(FOM) is found out to be -192.436 dBc/Hz @ 3 MHz and -180.1 dBc/Hz @ 100 kHz offset with a very low power consumption of 849.7 μW.

FOM (Figure Of Merit) is a novel performance yardstick of VCOs. Designing LC VCO circuit with desired specifications is highly time consuming and tedious job. In this paper CMODE (Combining Multi objective Optimization with Differential Evolution) optimization technique is used to design an LC VCO of optimal FOM with a target frequency of 2.5 GHz. The design parameters of LC VCO are obtained from the CMODE algorithm used in the MATLAB environment to optimize FOM. By using these parameters the LC VCO circuit is designed and synthesized in 90 nm CMOS technology in the Cadence Spectre Analog Design Environment(ADE). This VCO achieves phase noise of −119.7 dBc/Hz at 1 MHz offset while consuming 515 uW power with a tuning range of 10.53%. The FOM is obtained to be −190.26 dBc/Hz at 1 MHz offset. Hence the best performance index meeting the desired specifications is obtained in a single run of the algorithm.

The design of optimal analog and mixed signal (AMS) very large scale integrated circuits (VLSI) with lesser design cycle time is a challenging task for the integrated circuit (IC) designers. Voltage Controlled Oscillator (VCO) is a radio frequency integrated circuit (RFIC) having wide range of applications. This paper presents a new approach to design a ring oscillator (RO) with optimum performance with only one design cycle. The optimal figure of merit performance for a RO with a constraint of achieving a desired centre frequency is observed using a new technique which combines multi-objective optimization with differential evolution (CMODE). The RO is designed by considering the design parameters extracted from constrained CMODE in Cadence Virtuoso analog design environment (ADE) using gpdk090 library. The simulation results are compared with the CMODE predicted indices and are observed to be in good agreement with it. In this work RO circuits with 9 stages of inverters are considered to be designed for 2 GHz centre frequency with the limitations imposed by gpdk090 library. Results of exhaustive simulation and experimental studies for these ROs are presented here to verify the reduced design cycle time and superior performance offered by the proposed design methodology.

Digital ICs for electronic systems are fast realized on Field programmable gate array (FPGA). The reconfigurability of FPGA has made this mode of digital circuit synthesis more popular among the system designers. But unlike other ICs it provides a restricted hardware structure for circuit implementation and hence the computer aided design (CAD) software is also constrained. The placement being a very vital step in the design process needs to be performed optimally for high performance circuits. In this work novel techniques for placement based on simple particle swarm optimization (PSO), constricted PSO and time varying inertia weight (TVIW) PSO are proposed taking bounding box cost into consideration. The results of simulation reveal a competitive performance of the circuits implemented. The technique proposed here also offer faster convergence to a placement solution. The performance of a single BCD counter circuit is studied in details by using the different PSO algorithms. The netlist generated from the Xilinx design tool is used for placement and optimization results are reported here.

Field programmable gate array (FPGA) is a widely used programmable integrated circuit (IC) for fast realization of digital circuits in all electronic systems. Its reconfigurability has made this mode of digital circuit synthesis more popular among the system designers. But unlike other ICs it provides a restricted hardware structure for circuit implementation and hence the computer aided design (CAD) software is also constrained. The placement being a very vital step in the design process needs to be performed optimally for high performance circuits. In these work novel techniques for placement based on constricted particle swarm optimization (PSO), adaptive PSO and time varying inertia weight (TVIW) PSO are proposed. The results of simulation reveal a competitive performance of the circuits implemented. The technique proposed here also offer faster convergence to a placement solution. The performance of a single BCD counter circuit is studied in details by using the different PSO algorithms. The netlist generated from the Xilinx design tool is used for placement and optimization results are reported here.