86 results on '"Pradhan, Manoranjan"'
Search Results
2. Occurrence of Nonlinear Electron Mobility in GaAs/In x Ga1−x As Coupled Double Quantum Well FET
3. Analysis of Delay in 16 × 16 Signed Binary Multiplier
4. Occurrence of Nonlinear Electron Mobility in GaAs/InxGa1−xAs Coupled Double Quantum Well FET
5. Analysis of Delay in 16 × 16 Signed Binary Multiplier
6. Comparative Analysis of Decimal Fixed-Point Parallel Multipliers Using Signed Digit Radix-4, 5 and 10 Encodings
7. Dialdehyde cellulose as a niche material for versatile applications: an overview
8. Harnessing the potential of dialdehyde alginate-xanthan gum hydrogels as niche bioscaffolds for tissue engineering
9. Comparative Analysis of Partial Product Generators for Decimal Multiplication Using Signed-Digit Radix-10, -5 and -4 Encodings
10. Comparative Analysis of Decimal Fixed-Point Parallel Multipliers Using Signed Digit Radix-4, 5 and 10 Encodings
11. Asymmetric Doping‐Dependent Electron Transport Mobility in InxGa1–xAs/GaAs Quantum Well Field‐Effect Transistor Structure.
12. Synthesis Methods of Baugh-Wooley Multiplier and Non-restoring Divider to Enhance Primitive’s Results of QCA Circuits
13. A Novel and Efficient Design for Squaring Units by Quantum-Dot Cellular Automata
14. Synthesis and simulation study of non-restoring cell architecture layout in perpendicular nano-magnetic logic
15. Design of Conservative Gate and their Novel Application in Median Filtering in Emerging QCA Nanocircuit
16. Novel Robust Design for Reversible Code Converters and Binary Incrementer with Quantum-Dot Cellular Automata
17. A High-Speed Booth Multiplier Based on Redundant Binary Algorithm
18. Enhancement of electron transport mobility in GaAs/InGaAs asymmetrically doped narrow quantum well pHEMT structure
19. Intrusion Prevention System
20. An Improved Conversion Circuit for Redundant Binary to Conventional Binary Representation
21. An efficient redundant binary adder with revised computational rules
22. Energy-Hole Minimization in WSN Using Active Bonding and Separating Coverage
23. Intrusion Detection System (IDS) and Their Types
24. Intersubband effects on electron mobility in GaAs/ InxGa1-xAs Quantum well FET with asymmetric doping profiles
25. A Novel and Efficient Design for Squaring Units by Quantum-Dot Cellular Automata
26. Synthesis Methods of Baugh-Wooley Multiplier and Non-restoring Divider to Enhance Primitive’s Results of QCA Circuits
27. Novel Robust Design for Reversible Code Converters and Binary Incrementer with Quantum-Dot Cellular Automata
28. Design of Conservative Gate and their Novel Application in Median Filtering in Emerging QCA Nanocircuit
29. Structural Asymmetry related Nonlinear Mobility of Electron in InxGa1-xAs/GaAs Quantum well FET
30. Study of nonmonotonic electron mobility due to influence of asymmetric structure parameters in pseudomorphic heterojunction field effect transistors
31. A High-Speed Booth Multiplier Based on Redundant Binary Algorithm
32. Intrusion Prevention System
33. Energy-Hole Minimization in WSN Using Active Bonding and Separating Coverage
34. Intrusion Detection System (IDS) and Their Types
35. Improved Redundant Binary Adder Realization in FPGA
36. A Time Efficient Redundant Binary Adder with Modified Encoding Bits
37. Fast signed multiplier using Vedic Nikhilam algorithm
38. Mixture of Decimal and Binary Arithmetic Units For FPGA Based Architecture
39. Synthesis and simulation study of non-restoring cell architecture layout in perpendicular nano-magnetic logic
40. Analysis on Fault Mapping of Reversible Gates with Extended Hardware Description Language for Quantum Dot Cellular Automata Approach
41. A Universal Reversible Gate Architecture for Designing N-Bit Comparator Structure in Quantum-dot Cellular Automata
42. Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation
43. Time efficient signed Vedic multiplier using redundant binary representation
44. Design and evaluation of an efficient parity-preserving reversible QCA gate with online testability
45. Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Environment.
46. Efficient ASIC and FPGA implementation of cube architecture
47. A modified redundant binary adder for efficient VLSI architecture
48. Energy-Hole Minimization in WSN Using Active Bonding and Separating Coverage.
49. A novel vedic divider based crypto-hardware for nanocomputing paradigm: An extended perspective.
50. Design of magnetic dipole based 3D integration nano-circuits for future electronics application.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.