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An ultra-low quiescent current resistor-less power on reset circuit is presented in this brief. The circuit is used in energy harvesting systems to change boost converter from startup state to PWM modulation state. It integrates power on reset (POR) and brown out detection (BOD) functions without resistors or bandgaps overhead. Dual threshold detection (DTD) technology is used instead of a large size delay cell in generation of pulse signals. The circuit has been implemented in a $0.13{\mu }\text{m}$ standard CMOS technology. The active area and the quiescent current of the circuit are $154.4{\mu }\text{m}\,\,\times 26.8{\mu }\text{m}$ and about 1nA, respectively. Ultra-low quiescent current and small area make the proposed circuit suitable to be applied in low power applications like energy harvesting and beyond.

This paper proposes a highly reliable single-inductor multi-output (SIMO) converter for energy harvesting systems, which is controlled by the power management controller (PMC) including the hybrid starter, overcharging protector (OCP), and switch controller (SWC). The proposed hybrid starter employs the power-on-reset to accurately control the activated and deactivated moments of the SWC, thus generating a system supply voltage (VSYS) within the stable operating voltage range. The proposed OCP employs the diode-connection and Schmitt trigger schemes to monitor the voltage of a storage device (VSTG) in real time, thereby protecting the IC from being damaged without using either a capacitor or Zener diode, which causes the additional area or reverse leakage current, respectively. The proposed SIMO converter with the PMC was fabricated using 0.18-μm CMOS process. The measurement results show that VSYS values at the activated and deactivated moments of the SWC are 1.798 V and 1.510 V, respectively, both of which are within the stable system voltage range for 1.8 V devices. In addition, the measured maximum VSTG is 5.892 V, which is much lower than an absolute maximum rated voltage of 9.2 V for 5 V devices. Furthermore, the measurement results reveal that the hybrid starter allows the proposed SIMO converter to be properly restarted immediately after VSYS is shorted to ground, while the OCP safely protects the SIMO converter even when the storage device is removed from the IC while charging. Therefore, the proposed SIMO converter with the PMC is suitable for energy harvesting systems that require high reliability.

In this paper, a low voltage high accuracy 10- transistor power-on-reset circuit with brown-out-reset function is proposed. A native NMOS current reference based architecture is proposed to get high accuracy trip-voltage with a small area and power consumption. By adjusting the number of native NMOS transistors, a stable hysteresis window is obtained. Post-layout simulation results based on SMIC 55nm CMOS process show that the trip-voltage deviation of the proposed power-on-reset circuit is only 34mV under different temperature and process corners. Also, the trip-voltage of the proposed power-on-reset circuit shows great robustness to supply ramp time. The power consumption of the proposed circuit is as low as 36nW at 0.5V. Since the proposed power-on-reset circuit consists of only 10 transistors, the area is as low as 67.5µm2.

In this paper, the design of a power-ON-reset intellectual property (IP) block for the RD53 collaboration, a radiation hardening by design circuit to withstand the High-Luminosity Large Hadron Collider tracker radiation environment, is presented. In this environment, the performance of the IP block under radiation must be ensured for a total ionizing dose up to 500 Mrad and possible ions interaction for a linear energy transfer of 15 MeV/cm2/mg. To verify the radiation hardness of the presented circuit, an automatic single-event effect sensitivity tool (Analog Fault Tolerant University of Seville Hardware Debugging System) has been used to perform a complete analysis over it, and also several experiments have been performed to test the designed blocks and obtain the final IP qualification.

This paper presents a circuit for a power-on reset (POR). It uses a self-control mechanism to have the POR threshold different from the brown out reset (BOR) threshold. The change of threshold voltage happens after the output settles to its high value. It consumes a low current in the steady-state while functioning reliably to detect the BOR condition. It consumes 0.7uW under a 1.8V supply and provides a reliable POR/BOR circuit. Its simple architecture guarantees a good performance that has been verified by measurement. It covers wide supply ramp up and ramp down rates and occupies an area of 8250um2.

The single-event response of the RTG4 flash-based FPGA is characterized using 64 and 200 MeV proton sources. Several blocks are tested, including self-corrected triple module redundant (STMR) flip-flops with SET filter enabled and disabled, micro SRAM ($\mu$ SRAM), large SRAM (LSRAM), phase locked loop (PLL), serializer/deserializer (SERDES) and fabric double data rate controller (FDDRC). In-beam power on reset (POR) and reprogramming/verify are evaluated for the first time in proton environment.

To improve the accuracy and eliminate the bandgap reference circuit of conventional POR (power-on-reset) circuits, a low-cost, low-power, temperature-compensated POR circuit with precise trigger voltage is presented in this paper. The proposed POR circuit was designed and implemented in a 40nm CMOS technology. It achieves a 740nA quiescent current under 1.1V power supply, a 0.008mm2 active area, and a 350ppm/°C trigger voltage temperature coefficient from -40°C to 120°C.

In this paper, a high performance fully integrated 900 MHz analog front end for UHF RFID tag EPC C1 G2 standard protocol is presented. The proposed analog front end consists of a voltage regulation which consists of an RF to DC converter, voltage regulator circuit which regulated the DC voltage to prefer value (0.5V), ASK modulator/demodulator, a clock generator and a power on reset circuit. To minimize the power consumption of RFID transponder we propose the minimizing of the input voltage of the converter. Proposed regulator is designed under following conditions: RF frequency’s 900 MHz, 50 Ω antenna, a sensitivity of -24 dBm and a maximum power consumption of 1 µW. At 0.5 V proposed demodulator can demodulate the minimum input power -24 dBm for a modulation index of 37–100 % with 160 kbps data rates and consumes only12.74 nW. The power consumption and layout of the analog front end proposed in this work are about 1 uW and only 79 μm × 67 μm respectively. The simulation results dawn in 0.18 μm CMOS technology confirm the performance of the proposed analog front-end.

Miniaturized thin-film thermoelectric generators (TEGs) are emerging energy harvesting sources suitable for wearable and implantable applications. However, these sources usually exhibit large internal equivalent series resistance (ESR) that leads to low energy conversion efficiency and self-startup failures at ultra-low voltages. This paper presents a highly efficient boost converter with a novel Power-on-Reset (PoR) based self-startup circuit for systems harvesting the micro-scale thermal energy. The proposed circuit generates a train of pulses to kick start the self-startup through an internal feedback loop formed by the ESR of TEG, an auxiliary boost converter and a PoR circuit. The self-startup circuit is automatically disabled after the startup operation with a quiescent power consumption of 2 nW. A boost converter test chip with the proposed self-starter was fabricated in 65-nm CMOS technology node. It achieved a self-startup TEG voltage of 220 mV and a peak conversion efficiency of 76%. The minimum input voltage to sustain the boost operation is as low as 85 mV after the startup.

Design of a low-energy power-ON reset (POR) circuit is proposed to reduce the energy consumed by the stable supply of the dual supply static random access memory (SRAM), as the other supply is ramping up. The proposed POR circuit, when embedded inside dual supply SRAM, removes its ramp-up constraints related to voltage sequencing and pin states. The circuit consumes negligible energy during ramp-up, does not consume dynamic power during operations, and includes hysteresis to improve noise immunity against voltage fluctuations on the power supply. The POR circuit, designed in the 40-nm CMOS technology within 10.6- $\mu \text{m}^{2}$ area, enabled $27\times $ reduction in the energy consumed by the SRAM array supply during periphery power-up in typical conditions.

Ultra-low-power microcontrollers play an important role in system applications. In this paper, a Nano-watt Power-On Reset (POR) circuit with Brown-Out Detection (BOD) capability was proposed. The proposed circuit implemented in a 0.18 ​μm CMOS process, which contains long-reset and fast-reset time mode and provides a reset signal with approximately 3.314s and 22 ​ms, respectively. The embedded brown-out detection circuit can detect the event in time, as long as the abnormal supply voltage decreases to 1.4 ​V and the brown-out duration is longer than the microsecond range under 1.8 ​V–3.3 ​V. To further reduce power consumption, a bias state switching circuit and a Vpulse control signal generating circuit are proposed to reduce the static current in the start-up circuit and Schmitt triggers circuit. The circuit consumes less than 100 ​nA under 1.8 ​V–3.3 ​V power supply and occupies 110 ​× ​100 ​μm2 area.

In this paper, we present a bionic sensing system that monitor electromyography (EMG), electrocardiogram (ECG), vibration, and temperature for elderly care. The bionic sensor system contains analog front-end circuits (AFE) including sensor read-out circuit for bio-potential signal pickup, a piezo wave sensing circuit for vibration sensing, a low-power analog-to-digital (ADC) circuit with pulse-width modulation (PWM) digital signal output and a bandgap circuit for temperature tracking. For digital signal processing, we integrated a digital signal controller for AFE control and calibration, an ARM-like microprocessor (SYS32TM) for compression and communication. Finally, a phase-lock loop (PLL) circuit for system clock generating and power on reset, The analog and digital part of the chip has been tape-out separately. Analog circuit is integrated and tested with Xilinx Zynq System-on-Module (SoM). This verification platform is versatile for development while maintaining small form factor for user to wear the system while recording the bio-signals. The sensor system is currently used in elderly care and precision sport study.

The purpose of the Power-on Reset (POR) circuit is to reset the latches and flip-flops in an SOC to a known state when the supply is ramping up. During power-up, supply is not stable, and the ramp-up time can vary depending on the applications. A common approach is to generate a POR signal by comparing the supply voltage with a reference voltage. Pseudo dual/two port memories are used in graphic applications where parallel computing is prime factor instead of performance. IoT applications comprise significant image and video processing for which these memories are used. Conventional SRAM does not need a POR circuit but pseudo dual/two port memory face functionality issues without a POR circuit. Low-power applications, like Internet of Things (IoT) devices, comprise of SRAM arrays, sensors, and logic operating at sub-threshold or extremely low voltages. Conventional POR circuits also use a resistor divider circuit along with band gap reference. At these low operating voltages, generating a stable reference voltage is difficult because of band gap reference limitations and process variations. In this paper, we present multiple POR circuits that operates without using a reference voltage, making it robust against different sources of variation. First proposed circuit is self-timed, meaning the reset signal pulse-width varies according to the time needed to reset the latch. The designed circuit has been fabricated in 16 nm FinFET technology. Silicon validation shows that the proposed POR circuit works at a minimum supply voltage of 400 mv. Simulation verifies that the POR circuit is operational in sub-threshold region but is limited to 400 mV on silicon due to the operational voltage of additional testchip logic. Also, the POR circuit does not consume any dynamic power during normal operation of the SOC and has minimal area overhead of 21.3 µm2. Second proposed circuit is latch based self-feedback circuit which resolves limitations of the initial proposed circuit.

Several proposals of power-on-reset (POR) circuits have been reported in the literature, however only a few number of them offer the possibility to have configurable reset voltage levels. This paper proposes a POR circuit with programmable voltage thresholds allowing to operate in a wide number of applications. The circuit is based on a multi-level voltage reference using native transistors, which allows to have a reduced area and power consumption. The POR is designed in a $0.18 \mu \mathrm{m}$ standard-logic CMOS technology and occupies an area of $83\mu$ m x $68\mu \mathrm{m}$. Simulations results show a robust performance regarding temperature and process variations.

This paper presents a low-noise reset technique of an asynchronous charge-pulse-detecting pixel for single-photon X-ray imaging. The proposed slow-slope ramp (S2R) reset scheme provides a reset-noise-discharging loop circuit and effectively eliminates the residual noise charge stored on the sampling capacitor by extending the falling transition time of the reset signal. In addition, the presented S2R reset signal generation circuit accurately and effectively controls the optimum switching voltage and the falling transition time of the reset signal. The prototype detector chip was implemented by using a 130-nm complementary metal-oxide semiconductor (CMOS) process. With the quantitative analysis and the measurement results, we were able to verify that the reset noise was reduced exponentially, corresponding to the falling transition time of the reset signal. Based on the chip measurement results, the reset-noise level could be decreased by more than seven-fold by virtue of the proposed reset technique.

Display Omitted The resistive switching phenomenon is analyzed using a purposely in-house setup.The setup allows applying fast ramped voltages and measuring in the time domain.Set and Reset processes have been studied under a large range of ramp speeds.Voltage to provoke Set/Reset process increases as voltage ramp speed increases.A critical energy is needed to trigger the Set and Reset processes. The resistive switching phenomenon is analyzed using a purposely developed setup which allows fast ramped voltages and measurements in the time domain. Taking advantage of these capabilities, the Set and Reset processes in Ni/HfO2 structures have been studied for a large range of voltage ramp speeds. The results obtained show that Set and Reset voltages increase with voltage ramp speed. The use of time domain measurements has allowed concluding that a critical energy is needed to trigger the Set and Reset processes, independently of the biasing conditions.

In most literature related to reset control, the reset actions are triggered by continuous monitoring triggering reset conditions, which is not suitable for computer-based implementation. This paper considers periodic triggering reset control, where the reset actions are only triggered at periodically sampling instants. Hybrid system approach is given to analyze the asymptotic stability and L2 gain property, and less conservative switched system approach is presented for asymptotic stability analysis. The comparison of the two approaches is discussed. Moreover, novel reset conditions are given to improve the overshoot performance. Simulations are presented to support our results.

Three kinds of parameters are considered to speed up the read operation of phase change memory: bit line parasitic parameters, read transmission gate parasitic parameters and current mirror parasitic parameters. A set reference cell and a reset reference cell are used in the reference circuit. Simulated in 130 nm process, the read access time of 1-Mb phase change memory (PCM) is 6.7 ns. In Monte Carlo simulations, the worst read access time is 13.8 ns compared to conventional 85 ns.

A near-threshold low-complexity bandgap reference (BGR) and power-on reset (POR) hybrid circuit is implemented in 65 nm CMOS, with an ultra-low supply voltage of 0.55 V and power consumption of 2.5 μW. The BGR employing amplifier offset voltage and current matching, and the POR based on offset voltage matching and loop settling feature, are proposed. The circuit-level simulation results verify that the presented implementation, not only generates a stable reference voltage with the typical temperature coefficient of 120 ppm/°C and line-regulation feature of 3.3%/V, but provides a robust reset signal with power-on and brown-out detection function. The proposed near-threshold circuit has ultra-low power supply and design complexity, both for BGR and POR modules, when compared to the reported.

An ultra-lower-power reconfigurable voltage detector for indoor solar energy harvester is presented. The voltage detector monitors the solar cell voltage and sends out a flag signal if the solar cell voltage surpasses the triggering threshold of the detector. Instead of using a traditional dynamic comparator, this design is based on a power-on-reset (POR) circuit. A POR circuit has ultra-low quiescent loss and a fixed triggering threshold, which is determined by its topology and process. Our improvement is to use a feedback loop that allows the triggering threshold to be reconfigurable. The average quiescent loss of this POR voltage detector circuit is 2.774nW. Process and temperature variations can also be compensated by the feedback loop. The energy harvesting system is designed with a 0.18 p,m CMOS process. Equipped with the proposed voltage detector, the whole system achieves a 93.21% peak efficiency at 200μW input power.

A mixed-signal programmable Time-Division Power-On-Reset (TD-POR) circuit based on 8-bit Successive Approximation Analog-to-Digital Converter (SAR ADC) for accurate control in low-power hearing-aid System on Chip (SoC) is presented in this paper. The end-of-converter (EOC) signal of SAR ADC is used as the mode-change signal so that the circuit can detect the battery voltage and volume voltage alternately. And the TD-POR circuit also has brown-out reset (BOR) detection capability. Through digital logic circuit, the POR, BOR threshold, and delay time can be adjusted according to the system requirement. The circuit is implemented in SMIC 0.13 μm 1P8M CMOS process. The measurement results show that, in 1 V power supply, the POR, BOR, and volume control function are accomplished. The detection resolution is the best among previous work. With 120 Hz input signal and 15 kHz clock, the ADC shows that Signal to Noise plus Distortion Ratio (SNDR) is 46.5 dB and Effective Number Of Bits (ENOB) is 7.43 bits. Total circuit power consumption is only 86 μw for low-power application.

A power-on-reset (POR) circuit, which is an important block in mixed-signal integrated circuits, is used for the correct initialization of critical logic states in digital blocks of mixed-signal circuits. A POR circuit with precisely triggered threshold voltages is proposed. The circuit is designed in a 0.18 μm CMOS technology with a maximum 4 μA quiescent current. The output signal of the proposed circuit is also used to precisely detect whether the power supply is power-on or brown-out. The proposed POR circuit is insensitive to the power ramping time and tolerant to process variations. At typical corner, the proposed circuit reduces the quiescent current by more than 10x and layout area by 38% compared to the previously published designs.

The LHCb detector will undergo a major upgrade during the Long Shutdown 2 (LS2) of the LHC, including the full replacement of the main tracking system. The new tracker will use scintillating fibres to cover the complete area of the detector. Arrays of silicon photomultipliers (SiPMs) will be used to readout these fibres. Each array has 128 channels and is read out by the low-power ASIC PACIFIC specifically developed for this purpose. Each of the 64 channels of this ASIC comprise analog processing, digitization, slow control and digital output at a rate of 40 MHz. The analog processing consists of a preamplifier, shaper and integrator. An interleaved double gated integrator avoids dead time as one integrator is in reset while the other collects the signal. The two integrator outputs are merged by a track and hold to provide a continuous measurement. The output voltage is digitized using 3 comparators acting like a non-linear flash ADC. The three bits output is encoded into two bits and serialized (joining several channels). The design is complemented by auxiliary blocks such as voltage and current references, control DACs, power on reset (POR) circuitry and serializers. The slow control digital block consists in a 10 bit addressing I2C slave and a register bank for holding the configuration values. The PACIFIC ASIC has been designed using a 130 nm technology and several prototypes have been validated. The recently tested PACIFICr5 is expected to be the final version. Compared to its predecessor the PACIFICr4b, only minor changes were applied to the analog channel, some features added and the channel output switched from a single-ended to a differential link which serializes the data at 320 MHz.

An integrated reset controller (voltage supervisor) is designed and implemented. The system generates a reset signal, active while power supply brownout conditions are detected and for 250 ms after the supply voltage has increased to acceptable levels. The circuit is built in a Deep N-Well (DNW) 5V 0.35μm CMOS process, which provides good isolation between the on-chip devices and the substrate. The controller is based on a comparator, which uses a programmable voltage reference built with floating gate transistors. The voltage supervisor's operation is demonstrated by simulations and measurements.

The purpose of the Power-on Reset (POR) circuit is to reset the latches and flip-flops in an SOC to a known state when the supply is ramping up. During power-up, supply is not stable, and the ramp-up time can vary depending on the applications. A common approach is to generate a POR signal by comparing the supply voltage with a reference voltage. Conventional POR circuits also use a resistor divider circuit along with band gap reference. Low-power applications, like Internet of Things (IoT) devices, comprise of SRAM arrays, sensors, and logic operating at sub-threshold or extremely low voltages. At these low operating voltages, generating a stable reference voltage is difficult because of band gap reference limitations and process variations. In this paper, we present a POR circuit that operates without using a reference voltage, making it robust against different sources of variation. The proposed circuit is self-timed, meaning the reset signal pulse-width varies according to the time needed to reset the latch. The designed circuit has been fabricated in 16nm FINFET technology. Silicon validation shows that the proposed POR circuit works at a minimum supply voltage of 400mv. Simulation verifies that the POR circuit is operational in sub-threshold region, but is limited to 400mV on silicon due to the operational voltage of additional testchip logic. Also, the POR circuit does not consume any dynamic power during normal operation of the SOC and has minimal area overhead of 21.3pm2.

Reset control refers to an extension of linear controllers with switching mechanisms that reset their states to zero at each zero crossing of the inputs. In this paper we address practical implementations for a class of reset control, the Clegg Integrator (CI) and first order reset element (FORE). Some discrete-time formulation can destabilize the closed-loop system and must be avoided for successful implementation. Deployment of proportional gain + CI and standalone FORE is quite tractable for a low-order plant. Combination of linear and reset elements can help stabilize a more complicated system. Performance improvement can also be achieved by combining a reset scheme with state feedback design.

This paper proposes an Under Voltage Lock Out (UVLO) with zero static power consumption Power-on Reset (POR) circuit in a High-Voltage Integrated Circuit (HVIC). The HVIC with the proposed UVLO and POR circuit is fabricated using a 1.2 μm 650 V BCDMOS process. Experimental results show that the UVLO with POR circuit consumes very low static power; 411 μW at 15 V power supply. Moreover, the newly designed POR circuit works nicely regardless of high-side floating power supply rise time. The proposed circuit has good performance in terms of high-peak pulsating noise immunity. Therefore, this design is suitable for embedding in an HVIC with an integrated bootstrap diode for low power motor application and intelligent power modules.

We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a 60 × 30 μm² active area.

A 67-year old male with a dual-chamber pacemaker visited for a regular check-up. An unfamiliar message emerged on the display just after placing the programmer wand. We could recognize that the pacemaker had already been in the safe back-up mode of DDI, and the programmer prompted a re-initialization request. We are so surprised because there was no indication of device malfunction the day before in daily monitoring and a 12-lead electrocardiogram revealed normally working in the DDD mode just before checking the device. The pacemaker was immediately re-programmed to the former setting. This phenomenon has not recurred for 12 months. Keywords: Power-on reset, Electromagnetic interference, Pacemaker, Daily monitoring, Transmission interference

This work describes a use case study of a failing mixed-signal product that showed instability in the power-on-reset signal at cold temperatures. It is a marginal fail whose root-cause turned out to be larger than expected random variations in threshold voltage, that cause a mismatch between matched transistors in a comparator in a band-gap circuit. The fail was localized with OBIRCh in an SDL-like setup. Understanding the origin of the fail required transistor characterization, and device simulation. Further, FIB circuit-edit was used to prove that the fail could be resolved with a metal fix. This use case is representative of the multi-faceted aspects of failure analysis of mixed-signal devices. It highlights the cross-disciplinary team-effort required for the successful identification of the root-cause of a fail. Further, it is also a testament of the wide range of tools and techniques needed for the resolution of a failing product.

A novel method for the generation of the power-on-reset (POR) signal needed by the SOC is described. A POR signal is required for initialisation of the logical state in digital systems. To obtain an accurate trip point for the POR, generally a bandgap voltage reference is used along with additional logic. Such logic tends to limit the lowest possible trip point that can be achieved. The proposed implementation of POR is based on a modified bandgap circuit where a supply-dependent current is injected into the loop. In this case, the reference generation is not explicitly required and thus the trip point can be kept very close to the minimum supply required for the bandgap operation. This implementation also needs very small delay as the required delay is not dependent on supply ramp rates and can be made very small.

A high SET/RESET speed phase change memory cell with a NMOS selector is achieved by optimizing cell structure, material, programming circuit and testing method. An asymmetric T-shape cell structure increases the current density in the programmable region and reduces thermal diffusion in the cell. Super-lattice phase change material has a lower thermal conductivity. The circuit has a fast response and reduces the falling time of RESET pulse to 0.9 ns which enables a fast phase change operation of the memory cell. The testing system has good signal integrity and transmits the undistorted ultrafast programming enable signal to I/O ports of the chip. The optimized SET time is 50 ns and RESET time is 2 ns.

Many VLSI application system operate I/O supplies and core supplies and follow a predefined power up sequence. In this paper, a technique is presented to design low cost low power on reset circuit targeting low power applications. For designs operating on two supply (IOs etc.), most of the application requires power supply sequence free implementation and in order to do so, they need a signal to shut off the consumption and provide a fixed logic. The proposed circuitry helps in achieving the goal with very small consumption and area (2200 pm2). This circuit consumes maximum 3.2 μΑ static current in any state. The current consumption of proposed circuit is very low as compared to bandgap based POR circuit and very faster than inverter based conventional POR circuit. The proposed circuit works accurately for both ramp up and ramp down of power supply with varied possible transition times ranging from 10us to 10ms. Due to very low static current consumption and very fast response we can use this circuit in ultra-low power applications like IoT, imaging, sensing, biomedical and space. The proposed strategy has been presented with an implementation in 28nm CMOS FD-SOI technology and verified.

Using a current-mode multiple reset, a current-to-voltage(I-V) converter with a wide dynamic range was produced. The converterconsists of a trans-impedance amplifier(TIA), an analog-to-digital converter(ADC), and an N-bit counter. The digital output of the I-Vconverter is composed of higher N bits and lower bits, obtained from the N-bit counter and the ADC, respectively. For an input currentthat has departed from the linear region of the TIA, the counter increases its digital output, this determines a reset current which issubtracted from the input current of the I-V converter. This current-mode reset is repeated until the input current of the TIA lies in thelinear region. This I-V converter is realized using 0.35 ㎛ LSI technology. It is shown that the proposed I-V converter can increase themaximum input current by a factor of 2 N and widen the dynamic range by 6 N . Additionally, the I-V converter is successfully applied to aphotometric sensor. Keywords : Current-to-Voltage Converter, Current-Mode Multiple Reset, Trans-Impedance Amplifier, Dynamic Range

Review by Vladimir Orlov Nuclear Reset: Arms Reduction and Nonproliferation, eds. A. Arbatov and V. Dvorkin (Moscow: Moscow Carnegie Center/ROSSPEN, 2011), 511 pp. There are books which every speci...

A compact low-power on-chip power-on reset circuit with a brown-out detection capability is presented. With a pico-farad-order on-chip MOS capacitor, a long reset time is achieved. A prototype design implemented in a 0.18-μm CMOS process provides a reset signal with duration of hundreds of milliseconds. The embedded brown-out detection circuit can detect the event, as long as the brown-out duration is longer than the millisecond range. The chip consumes only 1 μA under a 1.8-V supply and occupies a 120 μm × 100 μm active area.

The reset band is a simple idea, and a must in practice, to improve reset compensation by adding extra phase lead in a feedback loop. However, a formal treatment of how the reset band can affect stability and performance of a reset control system is still an open issue. This work approaches the problem of the existence and stability of limit cycles of reset control systems with reset band. A frequency domain approach is given by using standard methods based on the describing function. In addition, closed-form expressions have been obtained for the describing function of arbitrary order full reset compensators with and without reset band.

In reset control systems, reset actions are triggered whenever a continuous signal crosses a hyperplane. In the computer-based implementation, however, the continuous triggering signal is sampled and the triggering condition is replaced by a discrete-time counterpart. In this work, we are interested in stability analysis and design of reset control systems based directly on discrete-time triggering conditions. First of all, a relationship between reset control systems and switched systems is established and some stability criteria are obtained. Secondly, it is revealed that a reset control system can be regarded as a hybrid system combining an underdamped baseline system and an overdamped reset mode. In addition, it is showed by example that the reset matrix, which is assumed to be zero in general, has significant effect on the damping ratio of the reset mode and thus can be adjusted to further improve the performance. Based on this observation, a three-step design procedure is proposed. A hard disk drive example is also investigated to demonstrate the proposed design procedure.

A novel power-on-reset (POR) circuit with simple architecture, small values of capacitances, ultra-lower power consumption, and self-adjustable delay time of reset pulse for passive UHF RFID tags is presented in this paper. A proposed delay element was adopted for the features of small capacitances and wide power supply rise time range. An inverter was used as a two-inputs logic device to simplify the architecture of the circuit. The technology used for design and simulation is SMIC 0.18 μm RF. Simulation results show that the circuit functions well under different process corners with different power supply rise time, and is able to generate a POR signal after the power supply is briefly powered off. The static power consumption is less than 30 pA. Moreover, the circuit operates properly along with other modules of analog front-end.

A compact power-on-reset pulse generator (POR-PG) circuit with a low-power and low-voltage operation capability is presented. Proposed POR-PG was fabricated in 0.5 μm 2P3M CMOS process. It was determined from simulations and measurements that proposed POR-PG works supply voltage levels between 1.8 V and 3.3 V and supply voltage rise times between 100 ns and 1 ms. POR-PG has very small silicon footprint. Layout size of proposed POR-PG circuit was 120 μm × 5 μm in 0.5 μm CMOS process. Comparing with other POR-PG circuits in the literature, proposed design enjoys lowest power consumption (< 6 μW), smallest silicon footprint, widest supply voltage range, and additional features such as brown-out detection capability. These achieved by using a unique cascadable POR delay element that consumes very low-power.