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The ability of packaging solutions to meet the high heat flux dissipation of power electronics relies heavily on effective thermal management strategies. During operation, power electronic devices generate high temperatures that can cause device degradation. To remove this heat from the devices, heat spreaders and cold plates are often used. However, the multiple layers that compose the module often lead to high thermal resistances that hinder heat dissipation and can give rise to interfacial failures. To address these challenges, this paper has investigated the direct integration of single-phase jet impingement cooling at the power electronic substrate level for improved thermal management. This method was evaluated using computational models, experiments, and analytical models. An optimization analysis was performed to determine the influence of various design parameters on the cooling system. Through the directly integrated cooling concept, a reduction of up to 25% in the total package thermal resistance compared to a conventional device package was achieved. In addition, the overall device temperature was reduced, and the thermal resistance was found to be between 0.21 °C/W and 0.47 °C/W for a heat dissipation of 100 W/cm2.

Available substrate materials for power module applications has been investigated for a long time. Though Direct Bonded Copper (DBC) substrates, nowadays, have been widely applied in power electronics applications, especially power modules, due to its superior performance in mechanical ruggedness, thermal conductivity, and isolation capability. Its cost and complicated requirements during fabrication processes are always concerns in industries. At the same time, flexible electronics has become a rapidly expanding area with commercial applications including displays, medical, automotive, sensors arrays, wearable electronics, etc. This paper will initiate an investigation on a dielectric material that has potential in high power wearable electronics applications. A recently developed ultra-thin Epoxy-Resin Based Dielectric (ERBD) substrate material which is suitable for power electronic applications, is introduced. The ERBD can be fabricated with thickness as low as 80μm, with more than 5kV DC isolation capability. Its thermal conductivity is 8W/mK, higher than similar product currently available in the market. ERBD is also able to be bonded with Cu plates on both sides. In this paper, the properties of ERBD are investigated. Scanning Electron Microscope (SEM) is applied to analyze the microstructure of ERBD, and its bonding interface with Cu plates. 3-omega and Transient Thermal Reflectance methods are employed to precisely measure the thermal conductivity. Dielectric constant and loss are measured at different frequency. Simulations are applied to correct the error from the fringing effect during the measurement. The leakage current of ERBD is also measured under different voltage and temperature with DC and AC condition. Reliability tests are conducted to examine the electrical isolation and shearing strength of ERBD. The suitability of ERBD for potential flexible power electronics application is discussed based on the results from investigation of properties of the dielectric.

This paper proposes a high power density SiC single-phase system potential for uninterrupted power supply applications. To get the high power density, the semiconductors, packaging, circuit topology, and thermal design are synthetically considered. To increase the switching frequency and reduce the size of the passive components, the SiC MOSFETs and diodes are chosen; to minimize the parasitic inductances and eliminate the snubbers, the SiC bare dies are packaged as the half-bridge (HB) modules; to remove the bulky dc-link capacitors, the full-bridge inverter and the active power filter are designed, and they are structured by using the fabricated SiC HB modules; and finally to dissipate the heat from such a compact enclosure in the cost-efficient way, the heat sink of the modules and the forced air cool system are well designed, and the thermal 3-D finite-element analysis model is built to survey the best cooling configuration. A 2-kVA prototype is built and tested, and the power density of the system is up to 58 W/in3 and the maximal efficiency is up to 98.3%.

This paper is focused on the advanced capabilities of Thick Printed Copper (TPC) technology used for power electronic substrate manufacturing. TPC technology is based on screen printing of special copper pastes on ceramic substrates and its firing in a nitrogen atmosphere. This technology can be used as an alternative solution to conventional metallization techniques such as DBC or AMB and enables wide-range interconnection capabilities which cannot be realized with these conventional techniques. TPC interconnection capabilities include multilayer structures, copper plated vias and integrated passive components. Parameters and reliability of above-mentioned TPC structures after accelerated aging and thermal shock cycling are described in this paper.

Low voltage power electronics applications ( TM 649 and Novec TM 774 – due to their lower pressure operation and low global warming potential compared to traditional two-phase coolants. The OL-PHP is investigated in vertical (90°) orientation with fill ratios ranging from 0.30 to 0.70. The results highlight the steady state operating conditions for each working fluid with instantaneous plots of pressure, temperature, and thermal resistance; the minimum potential bulk thermal resistance for each fill ratio and the effective thermal conductivity achievable for the OL-PHP.

Thin, compliant substrates are increasingly being used for flexible electronics, displays, wearable devices, etc. The dissipation of heat generated in such devices is likely to be an important technological challenge that has not been investigated sufficiently. This paper reports measurement of the out-of-plane thermal conductivity of materials for thin substrates, which is a key material property that governs thermal performance. One-dimensional, steady state thermal conduction is set up in the substrate of interest. Measurements of temperature gradient induced by an imposed heat flux result in the determination of out-of-plane thermal conductivity. Thermal contact resistance between the substrate and experimental setup is also obtained. Measurements are carried out on polyethylene naphthalate (PEN) and polyethylene teraphthalate (PET) substrates of varying thicknesses. Based on the measured thermal conductivity, simulations are carried out to compare the thermal performance of a thin substrate with a traditional substrate. Though flexible electronic devices dissipate very less power, the low thermal conductivity measured here, and the low substrate thickness indicate the critical need for thermal management of such devices. Results reported here indicate an upper limit on power dissipation in a flexible device compared to a traditional device for maintaining similar thermal performance. Measurements reported in this paper may help in the fundamental understanding of thermal transport and thermal management strategies in flexible electronics and displays. Display Omitted

Solid state electrochemical and chemo-resistive gas sensors have been used widely but can operate only under high temperature. For reducing the power consumption and optimizing the structure of the substrate of these sensors, we conducted device and circuit simulations using the COMSOL Multiphysics simulator. For assessing the effective types of substrate and heat isolation, we conducted three-dimensional thermal simulations in two separate parts; (a) by changing the shape of the contacting holes and (b) punching additional holes on the substrate. Thus, it was possible to achieve high temperature in the sensor end of the substrate while maintaining low power consumption, and temperature in the circuit.

This study explores the feasibility of single phase liquid channel cooling, pin fin cooling and spray cooling techniques for heat removal from a power electronic substrate. The substrate is formed using an AlN layer directly bonded to an AlSiC heat sink with a copper circuit layer. With a comparative assessment of the three cooling techniques using analytical modeling, the heat transfer coefficient and pressure drop in the package are optimized for a fixed coolant pumping power. Computational simulations of the three optimized geometries are performed to estimate the device temperatures and the maximum heat rates that can be dissipated with this pumping power. It is concluded that channel cooling yields the best thermal management performance and its use is recommended in the development of a packaged assembly.

Packages of commercial Gallium-Nitride power semiconductors present increasingly small dimensions to enable low parasitic inductance, increasing the heat flux density of the package and the challenges associated with their thermal management. This paper compares between Printed Circuit Boards and Direct Copper Bonded as substrates for a Gallium Nitride based half-bridge from a thermal and reliability point of view. The layout for both substrates was numerically optimized and a compact thermal model is proposed to compare both substrates. Measurement results confirm the modelling approach. Both substrates were also analysed regarding their maximum operating temperature and expected thermal cycling capability.

This paper presents a new and low-cost thermal interface assembly between a printed circuit board and a heat-sink that provides electric isolation on the whole surface, and thermal conduction where needed. The assembly relies on the association of an isolation and a spacer layer and a thermo-conductive gel. The bill of material is 8 times lower than a best in class thermal pad, and equivalent thermal resistance is 30% lower.

International audience; Motivated by the need for a multi-parameter sensing chip for water networks monitoring, we address here the specific case of a flow-rate sensor where the main challenge is the substrate material. Instead of using conventional low thermal conductivity materials such as glass, silicon has to be used. Indeed, a silicon substrate enables the co-integration of various kinds of sensors on the same chip as reported in this contribution. However, it increases the flow-rate sensor power consumption due to larger thermal leaks. We therefore design and study an optimized low power micro-machined thermal flow-rate sensor based on a silicon substrate and operating according to hot-wire anemometry. It can be considered as an alternative to other well established sensors for liquid flow-rate measurement when both the use of a silicon substrate and a low power consumption are needed.

The thermal challenges that emerge from the power dissipated by the integrated circuits inside a packaged microelectronics design play an important role in the behavior of the system. The need on higher component density with advanced performance in terms of speed and bandwidth, but in a narrower space may cause thermal, mechanical, and thermomechanical effects that can lead to degradation, limited performance and possible failure of the elements of the assembly. Such effects must be studied and their influence must be predicted prior to the chip fabrication in order to predict any degraded performance or failure mechanisms in the dies, the system components and the package; in this direction Multiphysics simulation tools can be used. By defining the appropriate design and giving the model parameters, material properties (such as thermal conductivity, material density and heat capacity) and the right boundary conditions, we are able to investigate the behavior of the modeled IC, system, or package and observe any possible areas of elevated temperature. In this direction, we have modeled, simulated and investigated the thermal behavior of an advanced integrated microelectronics system, including a System-in-Package component, a CMOS analog multiplexer, several NTC (negative temperature coefficient) thermistors, and two chip power resistors of the CP series. Experimental measurements and simulations have been conducted for the described model; the temperature gradient and numerical values of temperature in selected points of the system have been extracted during the simulations and have been compared with the experimental results under 1W applied power in the system. Moreover, several parameters and their influence to the system behavior have been studied during the simulations: the thermal conductivity of the components of the design (e.g. the FR-4 and the copper part of the substrate, the nickel part of the resistors) and the natural convection coefficient. The first parameter is a material property, while the second concerns the heat transfer mechanism in the system and is related to the power dissipation and cooling processes. Under 1W power (dissipated by the chip power resistor) the resulted temperature gradient in the design leads to elevated temperature values in the components. The closer the components are to the heat-source, the higher these numerical values are. The applied natural convection coefficient parameter have ranged between 5–25 W/m2K in our simulations, while reduced values of the thermal conductivity have been implemented due to impurities in the included materials in the real model.

Power electronics devices can be limited in operation, and lifetime by the ability to remove heat and maintain low junction temperatures. A common architecture for power electronics devices is a circuit soldered onto a direct-bonded-copper (DBC) substrate, which is attached to a heat spreader or and heat sink. The removal of some of these interfaces and materials, however, can reduce the overall thermal resistance and allow for the devices to operate at much higher power levels. One approach to do this is to directly cool the backside of the DBC power substrate. By sintering copper particles to the DBC, evaporative cooling can be integrated into the architecture without the need for another bond. In this study heat fluxes up to 75 W/cm2 were applied through a test chip attached to a 15 mm × 17 mm DBC substrate with varying thicknesses of sintered copper particles on the backside. The copper porous layer was partially submerged into deionized (DI) water in order to allow for capillary wicking and evaporative cooling from the backside. Heat was dissipated through the thermal test chip, while the junction temperature was measured. The surface temperature of the porous copper layer was measured with a FLIR thermal camera. From this set-up the evaporative heat transfer coefficient (HTC) was computed and the thermal resistance calculated. The thermal resistance was found to be in good agreement with numerical models. Overall, the thermal resistance was reduced by about half when compared to the conventional packaging design.

This paper presents a new design of a piezoelectric sensor that is miniaturized to monitor thermal problems in wide bandgap power modules, which anticipated to have the operation temperatures significantly higher than silicon power modules. Recent power modules, especially those employing wide bandgap power devices, suffer significantly elevated temperatures. The thermal sensor proposed herein is made of miniature piezoelectric pieces (which are solder-bonded on a direct bonded copper substrate) that convert thermal stress of the substrate to electrical voltage. Compared to previous designs, this design exhibits notably smaller size (more than 70 percent size-reduction) and excellent linearity (R⁁2 is about 0.96 close to 1.0) up to 220 degree Celsius, which is expected to be sufficient to monitor the maximum temperature observed in wide bandgap power modules. This achievement was enabled by (1) introducing a new piezoelectric material having a high Curie temperature, (2) improving sensor components and fabrication process, and (3) optimizing sensor locations.

Technology for high power devices has made impressive progress in increasing the current density of power semiconductor, system module, and design optimization, which realize high power systems with heterogeneous functional integration. Depending on the performance development of high power semiconductor, packaging technology of high power device is urgently required for efficiency improvement of the device. Power device packaging must provide superior thermal management due to high operating temperature of power modules. Here we, therefore, review critical challenges of typical power electronics packaging today including core assembly processes, component materials, and reliability evaluation regulations.

This paper deals with a method for low cost power electronic substratescreation, which are used for power electronic devices. Direct bond copper (DBC) technology is suitable for creating substrates with excellent thermal and electrical conductivity and good mechanical properties. Furthermore, DBC allows to create copper layers with the thickness of hundreds micrometers in one processing step. In this work, the muffle furnace is used for bonding copper to ceramic. Temperature profile, oxygen concentration during the bonding process and final treatment is described. The last part summarizes the results and presents advantages of this method.

In recent years, thermal management of electronic components is getting all the more important with the advance in downsizing and higher density packaging of electronics. The authors have proposed a concept of thermal network modeling to be used in estimating the temperature rise of small chip components to establish the copper pattern design rule. In this paper, based on the proposed concept, we discussed the relationship between the pattern heat resistance and various parameters, such as heat dissipation pad diameter and the board material thermal conductivity.

Power electronics packaging with a high level of compactness, robustness and versatility has recently become the focus of many technology development projects. In Europe main drivers for such efforts are e-mobility and "green" energy harvesting, which are promoted by European Commission and national authorities. One promising approach to realize a substantial level of size reduction and process flexibility in the packaging of power electronic systems is the embedding into the build-up layers of printed circuit boards. Conventional printed circuit board embedding -for low power applications- has meanwhile reached a considerable level of maturity and the number of products shipped per month are in the tens of millions. Using embedding technology for power electronic devices, however, is still challenging in many aspects. First of all for power applications the embedded system layout has to account for high currents and/or voltages and at the same time has to provide means to facilitate the power dissipation from the embedded components. PCB-substrates and modules therefore contain conductor traces with large cross sections and/or massive copper and ceramic structures in order to enable the required heat spreading. Such constructions are composed of materials with different CTEs. As a result considerable stresses prevails in the build-up layers. Since contrary to conventional PCBs the build-up of power modules are non-symmetrical a careful layout of embedded modules is necessary in order to avoid warpage of the package. Embedded power electronic components are semiconductor dies on the basis of silicon, silicon carbide and gallium nitride. The full area silver on the drain contact is compliant with the embedding approach. The gate and source contacts have to be reinforced by ten to fifteen micrometers copper. The required robustness and conductance of the electrical contact between chip and embedded substrate is achieved by back contact sintering using silver nanoparticles. Chips are mounted in a two-step process: they are placed in a high accuracy die bonder and pre-bonded, subsequently the contacts are sintered in a stack-lamination press at higher temperature and pressures. Front contacts between chips and the subsequent wiring layer are established by micro-via technology. During the embedding process power components are enclosed into a matrix of glass fabric and epoxy resin (prepreg). The choice of materials strongly depends on the foreseen use case. Subsequent definition of the conductor lines is an established printed circuit board process. A large variety of embedded power electronic modules has been realized so far. Size and performance of the systems differ accordingly: from modules with lateral dimensions of a few square millimeters containing two embedded components for low voltage and currents of up to 10 Amperes, to complex assemblies with 12 embedded semiconductors and a module area of several square decimeters for an operating Voltage of 600 V and a total power of up to 50 kW. The present paper will focus on recent developments in power electronic embedding using PCB technologies.

International audience; New wide-band gap semiconductors (SC) for power electronics such as SiC, GaN and diamond will allow higher power densities, leading tohigher operating temperatures. However, the surrounding materials will also undergo an increase in temperature, meaning that a parallel effort is needed in SC packaging technologies research. One of the essential components, the substrate, is used to insulate electrically the SC from the rest of the system, drain the generated heat and provide a path to connect the SC to the rest of the system. Direct bonded copper (DBC) and active metal-brazed (AMB) substrates have limited temperature and cycling operation, owing to the large differences in the thermal expansion coefficients between the ceramics and the metals. In this work we propose a new and original substrate technology based on two co-sintered ceramics: an insulating ceramic (AlN) and a conductive one (TIN). The microstructure, the chemical compatibility and the electrical properties indicate that the proposed substrate could operate at a temperature above 200 1C the current substrate technologies, which makes it particularly attractive for high-temperature power electronics applications.

In transportation applications, lower weight and volume of the power conversion systems is very important to achieve high power density, high efficiency, and superior performance. The thermal management of these power conversion units plays a significant role in reducing the weight and volume. The use of superconductive motors/generators, degaussing coils, energy storage modules, and cables has been considered to increase power density and efficiency. High-temperature superconducting (HTS) components combined with cryogenic power converters will provide significant benefits in the electrification of transportation and high power density power conversion systems. Cryogenic power converter modules offer other promising benefits over their room temperature counterparts in terms of reduced size and weight (i.e., increased power density) and improved efficiency, switching speed, and reliability. Such an integration could result in significant weight and space savings for next-generation mass transportation systems. In this article, the current research on cryogenic power electronics and superconducting motors/generators is discussed for future aircraft and ships.

International audience; Printed Circuit Boards (PCBs) are often used to mount gallium nitride transistors, as they offer good electrical performance. However, their thermal conductivity is not as good as with ceramic substrates. In this paper, we compare (experimentally and by simulation) both the electrical and thermal performances of GaN transistor mounted on PCBs and ceramic substrates, and we show that with a proper layout, the ceramic substrates can offer both a very good thermal management (thermal resistance 4 times lower than with PCB) and suitable electrical performance (parasitic inductances of 1–2 nH).

Power electronics packaging is required by almost all areas of power electronics applications, such as consumer electronics, automotive, aircraft, and military applications. Due to the significant heat dissipation from the switching behavior of power semiconductor devices, the interactions between thermal, electrical and mechanical aspects become very important to not only power electronics packaging design, but also long-term reliability of power modules. The interactions become more and more significant as the development of wideband gap power semiconductor devices has pushed the power modules to be able to operate at higher voltage levels, higher ambient temperature and higher switching frequencies. Power module development relies more and more on Finite Element Method (FEM) based multiphysics simulations, reducing design cycles, to couple the electrical, thermal and mechanical fields in simulations of different processes such as power module assembly, operations and reliability assessments. In this paper, several cases were introduced to demonstrate how multiphysics simulation worked in power module development. The first case was the simulation of the fringing effects to estimate the difference between practical parasitic capacitance value and theoretical parasitic capacitance value of double-side metallized ultra-thin ceramic. The second case was the pre-stress analysis of power module substrate made of a specific ultra-thin ceramic. The third case was the study of electrical field distribution and temperature distribution in a high voltage and high temperature Silicon Carbide power module. The last case was parasitics extraction of a PCB busbar for 50 kW Electric Vehicle Motor Drive Applications.

This paper deals with an adhesion measuring of samples prepared by prospective TPC (Thick Printed Copper) technology. The TPC technology is used for power electronic substrate manufacturing. Copper film is screen printed on alumina substrate and fired in nitrogen atmosphere. Oxygen level dependence on adhesion of copper film to alumina base and copper film solderability was observed in this paper.

Because of a rapid growth of worldwide energy consumption an economical use of power is a necessity to ensure the supply reliability. One key technology to realize sparing energy use is power electronics. The cost of power electronic devices became an important aspect in this application due to its broader use compared to the past. In recent years, high efficiency at a given lifetime with low system costs are the main focus for the development of power electronic system. To shorten development and qualification time of such systems simulation of electrical and thermal performance is done extensively in order to optimize cost, life time and efficiency of the device. The thermal resistance of the modules and in consequence the thermal resistance of the interconnect materials are important factors of the performance of such systems. The paper discusses different thermal conductivity measurements and die attach materials and substrate materials, along with the measurements with a package like system, containing the die attach material itself as well as interfaces of the die attach material to the die and the substrate. Different measurement methods available to determine the thermal performance in such a system. Some examples are the thermal diffusivity and the junction to case thermal resistance measurement. Measured and simulated values were compared and discussed.

Power density of converters have been dramatically increased through the innovations of packaging and integration technologies. Meanwhile, it also imposes more challenges on the thermal performances. An integrated power module packaged with magnetic component is proposed to improve both electrical and thermal performances. This paper presents the thermal analysis of the proposed power module. The magnetic component acts as both the filter inductor in the converter and the package of the power module. Benefiting from this package technology, the inductor can be designed with a bigger winding of lower resistance, thus generating less heat. The magnetic material has better thermal conductivity than plastic material used in conventional plastic packaged power modules; therefore, the power module has better thermal performance. Simulation is executed to show thermal effect of winding configurations. A thermal evaluation board is built to compare thermal performances of the proposed power module and two other commercial products. The proposed power module has 11°C lower than the other part with the same size.

The reliable operation of power electronic modules operating at high voltage is essential. The dielectric system within the power electronic module is reasonably simple, but must be worked as hard as possible to achieve the highest module power densities. It is well known that a critical location in a power electronic module in terms of high voltage performance is the edge of the substrate metallization where high electric fields can give rise to partial discharge within power electronic modules and can lead to eventual failure. This paper focuses on two particular issues. First, the performance of the gap between the substrate metallization on which the collector and emitter of the device sit is examined. Second, the performance of the substrate-gel interface is examined once samples have been thermally aged in a humid environment. © 2012 IEEE.

The performance of high power LEDs strongly depends on the junction temperature. Operating at high junction temperature causes degradation of light intensity and lifetime. Therefore, proper thermal management is critical for LED packaging. While the design of the heat sink is a major contributor to lowering the overall thermal resistance of the packaged luminaire, another area of concern arises from the need to address the large heat fluxes that exist beneath the die. In this study we conduct a thermal analysis of high power LED packages implementing chip-on-board (COB) architecture combined with power electronic substrate focusing on heat spreading effect. An analytical thermal resistance model is presented for the LED array and validated by comparing it with finite element analysis (FEA) results. By using the analytical expression of thermal resistance, it is possible to understand the impact of design parameters (e.g., material properties, LED spacing, substrate thickness, etc.) on the package thermal resistance, bypassing the need for detailed computational simulations using FEA.

This study elucidates the significance of thermal transient measurement based on structure function evaluation particularly on high power LEDs. The metal core printed circuit boards (MCPCBs) were redesigned with reference to the product datasheet. Aluminium nitride was employed as the dielectric material of the MCPCBs and thermal performance of copper and aluminium substrate with different substrate thickness has been reported in this paper. It was observed that the aluminium based MCPCBs performed better heat dissipation compared to the copper based MCPCBs. In addition, when two different thicknesses of the MCPCB substrates were compared, it was observed that the thicker substrate performed a lower thermal resistance compared to the thinner substrate MCPCB. The junction to board thermal resistance was determined using the standard transient dual interface method.

The goal of this study is to investigate packaging techniques for extreme environment (i.e., −50 °C to 250 °C) power electronics. Areas of interest include substrate materials and baseplate/heat spreader materials. Multiple substrate technologies are evaluated, including direct bond copper (DBC), direct bond aluminum (DBA), and active metal braze (AMB) substrates. When possible, varying thicknesses of ceramic and metal layers are included to determine if that parameter affects reliability. Within each material and thickness sample lot, different layout geometries and overall sizes are tested, again to determine if that specific parameter has an impact on reliability. In a power electronics application, these substrates are required to be attached to a baseplate/heat spreader for mechanical support and to improve thermal performance. Therefore, a smaller sample size of substrate materials was also tested for reliability when soldered to a metal matrix composite (MMC) baseplate. To evaluate the reliability of said materials, several inspection methods are utilized, comprising of scanning acoustic microscopy (SAM), optical microscopy, florescent penetrant inspection, cross section analysis, and optical profilometery. This paper will present the results of thermal stress studies on each of the materials under varying conditions. The conditions include: thermal dwell conditions of 250 °C in excess of 1000 hours and thermal cycling from −50 °C to 250 °C in excess of 1000 cycles. Current results will be presented and discussed.

One of the key issues for semiconductor chip packaging in microelectronics technology is the reliability of the chip packaging during harsh temperature change in practical use. Typically, a thermal expansion mismatch between a silicon chip and a package substrate causes cracks between interconnecting bumps after the thermal cycling when the wiring pitch becomes fine. To overcome this problem, we have developed a new dielectric film which has extremely low CTE (Coefficient of Thermal Expansion) with the almost equal value to silicon over a wide range of temperature. The film will realize thermally-reliable interconnection at package substrate fabrication and in high temperature applications.

Today, reflow soldering is a commonly used technique to establish large-area joints in power electronics modules. These joints are needed to attach large-area (>1 cm2) power semiconductor chips to the substrate, e.g., a direct-bond copper substrate, and the multichip module substrate to a copper base plate for heat spreading. Thermal performance, specifically thermal conductivity and thermomechanical reliability, of these large-area joints are critical to the electrical performance and lifetime of the power modules. Soft solder alloys, including the lead-tin eutectic and lead-free alternatives, have low thermal conductivities and are highly susceptible to fatigue failure. As demands mount for higher power density, higher junction temperature, and longer lifetime out of the power modules, reliance on solder-based joining is becoming a barrier for further advancement in power electronics systems. Recently, we successfully demonstrated lowtemperature sintering of nanoscale silver paste as a lead-free solution for achieving highperformance, high-reliability, and high-temperature interconnection of small devices (

The thermal behavior of power electronics devices has being a crucial design consideration because it is closely related to the reliability and also the cost of the converter system. Unfortunately, the widely used thermal models based on lumps of thermal resistance and capacitance have their limits to correctly predict the device temperatures, especially when considering the thermal grease and heat sink attached to the power semiconductor devices. In this paper, the frequency-domain approach is applied to the modelling of thermal dynamics for power devices. The limits of the existing RC lump-based thermal networks are explained from a point of view of frequency domain. Based on the discovery, a more advanced thermal model developed in the frequency domain is proposed, which can be easily established by characterizing the slope variation from the bode diagram of the typically used Foster thermal network. The proposed model can be used to predict not only the internal temperature behaviours of devices but also the behaviours of heat flowing out of the devices. As a result, more correct estimation of device temperature can be achieved when considering the attached cooling conditions.

This paper presents a novel piezoelectric sensor, which is integrated in power modules and analyzes temperature and thermal-mechanical stress in real time. Due to the increased power density, recent power modules are often exposed to high operating temperatures. Thus, it is critical to measure temperature and (related) thermal stress in power modules. The piezoelectric sensor proposed herein is fabricated by attaching PZT pieces on a direct bonded copper (DBC) substrate. Heat from operating power devices deflects power substrates and generates thermal stress, which is picked up by in-built piezoelectric sensors optimally located at critical locations. As the sensor locations are away from heat-generating power devices, their effects on device performance are negligible. Both simulation and experiment results demonstrate that the proposed sensor provides a very good linearity (R2= ∼0.99) in the temperature range from 40°C to 160°C. This sensor characteristics were consistent in different measurements. Therefore, our in-built piezoelectric thermal sensor facilities reliable in-situ monitoring of temperature distribution and thermal stress in power modules experiencing high temperatures.

The paper deals with the evaluation of robustness of high power Silicon Carbide power electronic modules under short circuit conditions. The severity of the tests is usually related to the achievement of the real failure mode which drives the device to withstand a big amount of energy. A short circuit analysis in hard switched fault (HSF) mode at different voltage levels showed a short circuit survivability time of over 10μs for some of the tested power modules meaning an achievement of similar and higher level of robustness if compared to their counterpart Si devices. Experimental tests will be shown and analyzed under different voltage conditions. The tests described in the paper have been targeted to evaluate the capability of the device to withstand extremely severe condition when they are used in a high power converter.

International audience; In order to merge low power and high voltage devices on the same chip at competitive cost, Smart Power integrated circuits (ICs) are extensively used. Electrical noise induced by power stage switching or external disturbances generates parasitic substrate currents, leading to a local shift of the substrate potential which can severely disturb low voltage circuits. Nowadays this is the major cause of failure of Smart Power ICs, inducing costly circuit redesign. Modern CAD tools cannot accurately simulate this injection of minority carriers in the substrate and their propagation in the substrate. In order to create a link between circuit design, modelling and implementation in innovative CAD tools there is a need to validate these models by measuring the high voltage perturbations that activate parasitic structures in the substrate directly on the chip. This paper presents an on-chip noise sensor dedicated to measurements of transient voltage fluctuations induced by high voltage activity and coupled by the substrate.

The epitaxial growth of GaN-based epilayers on sapphire substrates still remains as the main stream of manufacturing LED chips. The thermal load in high power and ultra-high power LEDs keeps being a big issue in engineering practices. Self-heating effects will result in efficiency droop, degradation of lighting qualities, activation of defects, etc. As an unavoidable problem accompanying LED's low external quantum efficiency, thermal management attracts great interests both in academic and industry areas. The laser lift-off technique was developed to decrease the thermal resistance of a LED chip. However, the process of laser lifting-off sapphire substrates will not only increase the cost, but also raise reliability concerns. Efforts paid on managing thermal issues in high power LEDs are never stopped. The present work intends to ease the thermal load in LEDs through adding heat dissipation channels, i.e. electro-depositing special copper films on the back of sapphire substrates. The special copper substrate is expected to be constructed by micro-/nano- dual sale crystals with highly (111) textures and naturally formed high density nano-twins. Such microstructures will endow the copper film characteristics of high strength, high thermal conductivity and high heat capacity. The highly (111) texture also can help to control the solder joint microstructures. In this paper, process validation and device fabrication are done to verify the applicability to ease thermal load through electrodepositing the special copper film on the sapphire substrate. Experimentally, copper films with a degree of 95% (111) texture are successfully obtained. Microstructure analyses show that the copper grains are constructed by high density nano-twins. In other words, the copper grains present a micro-/nano- dual scale structure, which has been confirmed to have high strength, high thermal conductivity and high electrical conductivity in literatures. Based on the electroplated highly (111) textured copper films, high power LEDs with a thermal resistance below 3.0°C/W are achieved experimentally.

International audience; In order to merge low power and high voltage devices on the same chip at competitive cost, Smart Power integrated circuits (ICs) are extensively used. Electrical noise induced by power stage switching or external disturbances generates parasitic substrate currents, leading to a local shift of the substrate potential which can severely disturb low voltage circuits. Nowadays this is the major cause of failure of Smart Power ICs, inducing costly circuit redesign. Modern CAD tools cannot accurately simulate this injection of minority carriers in the substrate and their propagation in the substrate. In order to create a link between circuit design, modelling and implementation in innovative CAD tools there is a need to validate these models by measuring the high voltage perturbations that activate parasitic structures in the substrate directly on the chip. This paper presents an on-chip noise sensor dedicated to measurements of transient voltage fluctuations induced by high voltage activity and coupled by the substrate. Index Terms— on-chip sensor; Smart Power IC; substrate noise coupling; electromagnetic compatibility; substrate parasitic bipolar structures; I. INTRODUCTION Nowadays, many segments of microelectronics move towards monolithic system integration merging on the same IC (Smart power ICs) low voltage analog and/or digital parts with high voltage parts using power transistors. Substrate coupling in Smart power ICs occurs when parasitic bipolar structures (with unpredictable size and location) are activated after an injection of current into the substrate due to internal switching activity or external noise coupling. When low power analog and digital applications are integrated with high voltage (HV) devices on the same IC, these side effects become very important and hurtful to the circuit operation. In turn, designers have to rely on empirical basis for the design strategy, which is expensive and time consuming. Today, when simulating circuits with HV-MOSFETS devices, their specific SPICE models are used in every CAD tool but these models do not address generation of these parasitic substrate currents of minority and majority carriers. AUTOMICS project [1] aims at providing SPICE models, once implemented in CAD tools, will allow optimizing high voltage and high current capability, EMI-EMC performance with respect to substrate parasitic robustness.

A simple model for heat generation and heat spreading, and temperature rise of the active region of a power semiconductor switch is presented by properly accounting for semiconductor and package thermal and heat capacity parameters. The model is used to estimate the effect of finite substrate thickness in silicon and wide bandgap (WBG) power switching devices on junction temperature rise. Whereas 4H-SiC power devices show superior thermal performance compared to either GaN or silicon power devices, calculations suggest the need to thin down the current state-of-the-art 4H-SiC substrates by at least a factor of two, and the need to increase thermal conductivity of GaN substrates. The model is also used to estimate the power-handling capability of power switch modules, and the experimental data is shown to be in good agreement with the theoretical model for 1700V/25A 4H-SiC JBS power diodes.

The goal of this study is to compare thermal parameters of different substrates for high power light-emitting diodes (LEDs) with emphasis on the cost and size. The standard glass epoxy substrate (FR4) with thermal vias and insulated metallic substrate (IMS) were chosen as suitable samples for this study. Thermal simulation and thermal start-up were performed in order to evaluate the heat dissipation of high power LED.

A two-resistor model of the power chip in automotive electronic control units is presented based on Inverse-Method Algorithm. According to the results of simulation and experiment, the determination method of the two-resistor model parameters is provided, and the effect of the thermal resistances and printed circuit board copper coverage on the simulation precision of the power chip case temperature are discussed. The thermal simulation method and results proposed in this paper are of useful reference value to the thermal design of automotive electronic control units.

In this work we present the results on a reliability study on SMD components mounted on an organic power electronics substrate. The substrate technology has been developed to meet the needs of high ampacity and thermal conductivity with an organic substrate material. Therefore a thick structured copper core was introduced throughout the entire substrate size (see fig. 1). On top of the copper core common FR4 multilayer structures are realised to create a typical SMD PCB surface. The bottom of the copper core was covered with one prepreg with a high thermal conductivity and one copper layer to be able to connect to a heat sink. The copper core becomes structured to enable the use as the layer for conducting high currents. Therefore insulation trenches were manufactured and plugged with a polymer.

The increased heat generation in power electronic components can greatly reduce the reliability of the components and increase the chances of malfunction to the components. A good understanding of the thermal behavior of these components can help in deciding an effective thermal management scheme. Recognizing the inherent need for the thermal design of the active integrated power electronics modules, this paper assesses various possibilities of integrated thermal management for integrated power electronics modules. These integrated thermal management strategies include employing high thermal conductivity materials as well as structural modifications to the current module structure while not adding complexity to the fabrication process to reduce the cost.

Power MOSFETs in surface-mount device (SMD) packages are used in circuit topologies with higher power density. Thermal modelling of these MOSFETs is necessary for estimating the allowable power loss. Use of explicit heatsink is not convenient in SMD MOSFETs compared to the through-hole packages. Hence, in many cases, it may be necessary to rely on natural air-cooling for the SMD MOSFETs. Paralleling of these MOSFETs is required in many applications for reducing the conduction losses and limiting temperature rise. In this paper, a prototype PCB and test setup are presented for obtaining the thermal model for paralleled SMD MOSFETs. It is also explained that the conventional correlations used for calculation of convective heat transfer coefficients do not apply to these devices, necessitating the need for experimental investigation. The thermal resistances obtained experimentally are significantly different compared to the datasheet values. A thermal resistance model is arrived at by using the results from experimental setup. It is shown that a thermal model based on a prototype circuit-board is an important step in optimizing the layout of the power converter.

This paper describes the development of a thermal flow simulation method for the design of electronic equipment. In the proposed sequence of analyses, the electric circuit analysis for estimating power loss in power semiconductor devices was integrated with the thermal analysis. The method was applied to the thermal design of a new switch mode power supply (SMPS). The analysis was carried out using a commercially available computational fluid dynamics (CFD) code. In reducing actual structural organizations of the printed circuit board (PCB) and the power semiconductor devices to simpler models, the method of experimental design (MED) was employed. Following the prescription of MED, the PCB was treated as a simple plate having the same thermal conductivity as epoxy resin, and the power semiconductor devices were modeled by hexahedral resistance network. The heat sources were a field effect transistor (FET) and a diode. Computation of power loss from the FET and the diodes is described and the accuracy of different estimation methods is discussed. The difference between measured and calculated temperature rises of the power semiconductor devices was found to be within approximately 10 K. © 2004 Wiley Periodicals, Inc. Heat Trans Asian Res, 33(8): 473–489, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/htj.20037

The thermal conductivity and microstructure of Si3N4 ceramics used for power electronic substrate were studied in present paper. Thermal conductivity of Si3N4 ceramics sintered at different temperatures varied greatly. The microstructure of the specimens was studied with X-ray diffraction, EDS and transmission electronic microscope to reveal the difference in thermal conductivity. The experimental results showed that microstructure of Si3N4 ceramics sintered at different temperatures had different components in their grain phase and grain boundary phase, while electrical properties showed not much difference with different sintering temperatures.

A process for manufacturing a directly bonded aluminum/alumina (DBA) power electronic substrate was developed in the present work. The bonding interface of the substrate was studied using transmission electron microscopy to elucidate the bonding mechanism of aluminum to alumina. The bonding strength, the wetting ability, the wire bonding capacity, the break down voltage and the thermal resistance of the DBA substrate were studied in comparison with those of a widely used directly bonded copper/alumina substrate. The results show that the DBA substrate has an excellent thermal cycle tolerance, and it is most suitable for assembling power electronic devices that are used under severe condition such as in vehicles.

In the recent few years, high power electronic becomes one of the fastest growing market segments of semiconductor industry, because of the strong demand of high energy conversion efficiency and low energy loss, for the green environment protection. The major applications are motor drivers, UPS, PV inverters, hybrid/electric vehicle, rail traction and wind turbines…etc. Those applications are typically operating at very high voltage (> 200V) and high current (> 50A), and also need to operate under high temperature and harsh environment. Therefore, the circuit boards for such applications must achieve outstanding characteristics in terms of electrical, thermal, and mechanical performance, in order to provide reliable functionality during operation. Ceramics are no doubt the unique material that can offer excellent performance to survive at such operation conditions, and can be used as the core material of the circuit board for power modules. Therefore, in order to further understand the advantages and disadvantages of each ceramic technology, such as DBC, DPC, and thick film substrates, a comprehensive comparison study on reliability, thermal, and electrical performance were discussed.

Electronic components are continuously getting smaller. They embed more and more powered functions which exacerbate the temperature rise in component/board interconnect areas. Their design optimization is henceforth mandatory to control the temperature excess and to preserve component reliability. To allow the electronic designer to early analyze the limits of their power dissipation, an analytical model of a multi-layered electronic board was established with the purpose to assess the validity of conventional board modeling approaches. For decades, a vast majority of authors have been promoting a homogenous single layer model that lumped the layers of the board using effective orthotropic thermal properties. The work presents the thermal behavior comparison between a detailed multi-layer representation and its deducted equivalent lumped model for an extensive set of variable parameters, such as effective thermal conductivities calculation models or source size. The results highlight the fact that the conventional practices for Printed Circuit Board modeling can dramatically underestimate source temperatures when their size is very small.

The demand for power electronic systems to operate in harsh environmental conditions has increased over the past 20 years. These environments include those relating to deep oil-well drilling, automotive and aerospace applications. The miniaturization of the power module along with higher power densities have created elevated stress levels on ancillary subsystems, specifically the control circuitry. This study develops first-order methods and models to assess the solder interconnect reliability of critical components on the control circuitry in power electronic systems. Thermal and reliability simulations based upon Physics-of-Failure modeling techniques were conducted on a 2.2 kW variable-frequency drive to evaluate the susceptibility of component level failure mechanisms. CalcePWA, an interconnect reliability modeling software tool, was used as the primary vehicle to conduct these simulation models. A power cycling apparatus was constructed in order to calibrate the reliability models through accelerated testing of the drive.