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none 12 si In this paper we present D.A.V.I.D.E. (Development for an Added Value Infrastructure Designed in Europe), an innovative and energy efficient High Performance Computing cluster designed by E4 Computer Engineering for PRACE (Partnership for Advanced Computing in Europe). D.A.V.I.D.E. is built using best-in-class components (IBM’s POWER8-NVLink CPUs, NVIDIA TESLA P100 GPUs, Mellanox InfiniBand EDR 100 Gb/s networking) plus custom hardware and an innovative system middleware software. D.A.V.I.D.E. features (i) a dedicated power monitor interface, built around the BeagleBone Black Board that allows high frequency sampling directly from the power backplane and scalable integration with the internal node telemetry and system level power management software; (ii) a custom-built chassis, based on OpenRack form factor, and liquid cooling that allows the system to be used in modern, energy efficient, datacenter; (iii) software components designed for enabling fine grain power monitoring, power management (i.e. power capping and energy aware job scheduling) and application power profiling, based on dedicated machine learning components. Software APIs are offered to developers and users to tune the computing node performance and power consumption around on the application requirements. The first pilot system that we will deploy at the beginning of 2017, will demonstrate key HPC applications from different fields ported and optimized for this innovative platform. open Abu Ahmad, Wissam; Bartolini, Andrea; Beneventi, Francesco; Benini, Luca; Borghesi, Andrea; Cicala, Marco; Forestieri, Privato; Gianfreda, Cosimo; Gregori, Daniele; Libri, Antonio; Spiga, Filippo; Tinti, Simone Abu Ahmad, Wissam; Bartolini, Andrea; Beneventi, Francesco; Benini, Luca; Borghesi, Andrea; Cicala, Marco; Forestieri, Privato; Gianfreda, Cosimo; Gregori, Daniele; Libri, Antonio; Spiga, Filippo; Tinti, Simone

The mortality rate due to cardiac abnormalities is enormous, making the development of wearables to monitor functioning of the heart of paramount importance. In this paper, wepresent a resource efficient and low power architecture using Integer Haar Wavelet Transform for the complete delineation of ECG signal. The novelty of the algorithm lies in the use of single scale wavelet coefficients to delineate P-QRS-T features making it computationally simple. The proposed architecture is implemented using Xilinx FPGA ZedBoard Zynq™ − 7000 platform, and utilises only 4.38% of the available resources. It is synthesised using 180 nm CMOS technology consuming 0.88 μ W power, making it area as well as power-efficient for the wearable IoT healthcare devices.

To overcome short-term input energy fluctuations, and to offer complete 24-h energy solutions based on renewable resources such as solar and wind, energy storage devices are mandatory. A relatively new storage family is the supercapacitor (SC), which were developing rapidly over the last 15 years, and are yet to compete with rechargeable batteries. Today with three different commercially available SC families developing rapidly, with 1–70 000 F per single cell, at least one of them is reaching the specific energy of lead-acid batteries. All new families of SCs have charge/discharge life cycles of several orders larger than rechargeable battery chemistries, and their usage in energy storage systems is rapidly advancing. The SC-assisted converters are a new family of very low-speed converters, where a power electronic building block is combined with an SC bank to achieve high end-to-end efficiency, with the added advantage of dc-uninterruptible power supply (UPS) capability within the converter. This article provides an overview of the new SC-assisted loss management theory applied to SC-assisted converters, with practical examples of implementation useful in renewable energy systems such as SC-assisted low dropout regulator, SC-assisted LED, SC-assisted server rack power architecture, and SC-assisted wide-input inverter. In developing these new converters, useful in renewable energy systems, SCs are considered as a new device family with five to six-order larger capacitance for the same canister size, helping the achievement of the long time constant circuits.

Designing power supplies, especially for power adapters, requires that the designer possess a particular level of expertise and insight into implementing the best architecture. This level of expertise is especially relevant when using a power architecture known as Active Clamp Flyback (ACF). This article will demonstrate, to designers, a practical design method to obtain a reliable, robust, efficient, and high power density, ACF architecture with the bonus of fast time-to-market. Designers can eliminate that conventional Resistor Capacitor Diode (RCD) snubber circuit in their flyback converter design and learn the more efficient ways of active clamp operation. The ultimate solution is an all-Silicon design in a single package which also includes continuous advanced adaptive cycle-by-cycle digital control circuit for im proved performance over varying line/load/temperature as well as component tolerances. The outcome of the proposed design is high efficiency and power density, low EMI, and stringent line/load regulation.

In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter using block least mean square algorithm (BLMS) based on systolic array architecture with parallel data processing units is presented. A high level of parallelism is observed in the proposed work, improving the efficiency of variable coefficient FIR structure. The parallel look-up tables (LUT) in combination with the shift accumulator emulate multiply and accumulate operations. In order to reduce the number of clock cycles, B parallel LUTs are used, where B is the coefficient size. The block processing in BLMS Adaptive FIR Filter of block length L gives L times high throughput. This structure accepts block of input samples and generates block of output in each clock cycle. It requires less number of registers for computing filter output response and weight increment vector as memory reuse concept is used for implementing registers. This structure doesn’t require multiplexer. The designed DA based FIR filter is implemented on FPGA. The implementation results shows that the manuscript presents a high speed and low power architecture. The proposed structure provides 17.3 times less power and 9.5 times increase in throughput when compared to existing designs.

The widespread adoption of cloud computing has been driven by technological advantages, such as pay-as-you-go plan, scalability and high availability. From cloud service providers point-of-view, managing all these high customer expectations is a growing and critical challenge. This paper examines the relationship among energy infrastructure architectures, checkpoint mechanisms, and availability of software applications in a cloud data center. We consider four power architectures, three checkpoint mechanisms (cold, warm, and hot) with different sizes of files, and two applications (Video on Demand and digital library). For that, we propose a set of stochastic models (based on Petri Net and Reliability Block Diagram) and perform sensitivity and availability analysis. From results, we note that the power architecture has a great impact on application availability while the checkpoint mechanism only impacts with the application has a low mean time to failure value.

Isolated high-output-current DC/DC converters are critical technologies for future datacenter power architecture. LLC converters with matrix transformers are suitable for these applications due to their high efficiency and high power density. Previously, The Center for Power Electronics Systems (CPES) proposed a PCB-winding based matrix transformer for a 400V/12V 1MHz unregulated LLC converter. This paper aims to further improve the efficiency of the converter, without compromising on the power density, by optimizing the switching frequency of the converter, and mitigating the current sharing issues associated with center-tap rectifiers and shielding in matrix transformers with multiple outputs. The elimination of these issues is critical because they can lead to non-uniform increases in device temperatures and a reduction in the overall efficiency of the converter. The proposed improvements are verified by developing a 1 kW prototype with a peak efficiency of 98.05% and a power density of 940 W/in3

Power consumption of data centers has increased rapidly over recent years. Of late, 48 V power architecture has attracted more interest in data centers as it offers more efficient architecture. This paper focuses on the implementation of the DC-DC stage of the power supply unit for narrow range 48 V datacenter bus architecture. The paper presents a nearly 99% efficient 400 V-48 V LLC with a very high power density and low profile fully integrated on PCB. The LLC topology is chosen as it can achieve soft-switching, allowing one to push the switching frequency and increase the power density. A matrix of four transformers is used to reduce the termination loss of the secondary synchronous rectifier and achieve better thermal management. The number of secondary turns is optimized to achieve the best trade-off between winding loss, core loss, and power density. A matrix of four resonant inductors is also designed to reduce the proximity effect between inductor windings and reduce inductor PCB winding loss. The converter integrates a matrix of four transformers and resonant inductors on a 6-layer PCB and single-core for easier manufacturability and lower cost. A prototype is tested for the proposed converter at 250 kHz with 98.8% efficiency and 600 W/in3 power density with an 11 mm profile.

Universal serial bus power delivery (USB-PD) chargers are more attractive to consumers with multiple output ports. Existing multiple port charger designs take multi-stage approach thus increase power loss and charger size. Also, ports are normally designed with different power capability thus the high-power port becomes under-used if the connected device is fully charged while the other lower power ports cannot take over the unused power. This is mainly limited by the power architecture design. This paper addresses this issue by presenting a multiplexing based multi-port quasi-resonant flyback converter. The design achieves true power-sharing with high efficiency, small size, and simple analog implementation. This paper discusses the operating principle and design considerations. A GaN-based 60 W dual port charger verifies the proposed scheme while achieving 76% size reduction and 1% efficiency improvement than state-of-the-art.

In recent years, the use of distributed power sources, such as photovoltaic power generators and fuel cells, has become widespread. In particular, next-generation power distribution systems for residences based on direct current (DC) power supply and distribution are being actively researched in Japan. In this context, this paper investigates the effects of operating home appliances with a DC power supply using a special winding transformer on each device were investigated. To this end, a smart house equipped with DC power supplied by a transformer with a special winding structure was configured. Experimental observations confirmed that all digital home appliances exhibited proper functions on the aforementioned DC power architecture.

Power consumption of data centers is increasing rapidly over recent years. Recently, 48V power architecture has attracted more interest in data centers as it offers more efficient architecture. This paper focuses on the implementation of the DC-DC stage of the 3 kW power supply unit. Full-bridge regulated LLC converter is designed with a matrix of two transformers. This paper focuses on the magnetic design of the PCB-based transformer and resonant inductor of the LLC converter. The dimensional effects on core loss are discussed and evaluated. A matrix of two transformers implemented on UI core with rectangular core shape is proposed to minimize the eddy core loss of the transformer core. The termination of the secondary Full-bridge rectifier is also optimized to reduce the conduction loss of the transformer. A low-profile prototype of the designed converter is demonstrated with a peak efficiency of 98% and power density of 700W/in3.

Medium-voltage DC (MVDC) distribution system is considered as the promising power architecture of future shipboard power system. Fault-tolerance ability is of great importance for power system on ships. In this paper, zonal DC-DC conversion system based on modular multilevel converter (MMC) and three-phase bridge rectifier are proposed with its hierarchical fault-tolerant scheme. The topology configurations of the front-end MMC with multi-winding medium frequency transformer (MFT) under normal and post-fault circumstances are presented. The recon-figuration scheme and fault-tolerant control strategy are also proposed to ride-through sub-module (SM) level fault, phase level fault and bus level fault. Based on the hierarchical fault-tolerant scheme, redundant configuration of the MMC sub-module is further analyzed with the hierarchical reliability modelling. The effectiveness of the proposed control strategy is verified by the experimental results.

Large-scale datacenters are facing increasing pressure of capping their carbon emission and power cost. Many leading-edge studies have started to explore server clusters running on multiple power sources. Existing approaches do not sufficiently consider the fine-grained power delivery to satisfy diverse requirements in datacenter, especially in the multi-tenant/colocation datacenter, which may yield low energy utilization. To address the emerging trend and new requirements, this article proposes a novel Datacenter inner Power Switch Network ( DiPSN ) to improve datacenter power efficiency and user satisfaction. DiPSN is a reconfigurable and easy-to-scale-out power architecture, which enables datacenter to distribute various power sources in a fine-grained manner. Moreover, a tailored machine learning based power source management framework is proposed for DiPSN to dynamically optimize user customized performance metrics and maximize datacenter revenue. Compared with conventional single-switch power distribution system, our DiPSN can be configured to improve solar energy utilization by 39.6 percent, reduce utility power cost by 11.1 percent and improve workload performance by 33.8 percent. Meanwhile, our design can extend battery lifetime by 9.3 percent. This work could provide valuable guidelines for designing heterogeneous power distribution architecture and management methodology in datacenters for improving user-customizable efficiency, sustainability and economy.

Maritime applications have found in the integration of the electric power system a way to further improve efficiency and reduce the weight of new electric ships. This movement has led scientists to integrate smart management systems to optimize the overall behavior of the grid. In this context, power electronics play a key role in linking the different elements of the power architecture. Moreover, the transition toward a dc distribution, which has already been established in other applications, is being regarded as a promising alternative to ease the integration of renewable sources, batteries, and the ever increasing number of dc loads. In this paper, blackbox models are proposed as a tool to foresee the effect of these complex interactions, overcoming the lack of detailed information about the power converters. Large-signal strategies are proposed in order to consider nonlinearities in the static and dynamic behavior of the converters. An accurate model of the physical layer is essential to allow intelligent systems to take the most out of the system performance. This approach offers the opportunity to study the dynamic response of complex interconnected systems, tune the system-level controllers, design protections, or assess the compliance of the system dynamics with the standards. Experimental results are included in order to validate the proposed method.

Light-emitting diode (LED) technology has become one of the most important luminaire, due to its environmentally-friendly behavior, high efficiency, quality of light and large lifespan. Different LED drivers based on power converters have been presented. However, most of these solutions are focused principally on low-power lighting systems, above 100 W. This paper presents a novel modular solution for 1200 W LED driver with very high efficiency. The proposed power architecture is based on a cascade connection of a DC transformer (DCX) and a partial power converter (PPC). A comprehensive comparison between different PPC configuration is presented and supported by simulations to validate the theoretical results.

Energy harvesting devices (EHDs) are becoming extremely prevalent in remote and hazardous environments. They sense the ambient parameters and compute some statistics on them, which are then sent to a remote server. Due to the resource-constrained nature of EHDs, it is challenging to perform exact computations on streaming data; however, if we are willing to tolerate a slight amount of inaccuracy, we can leverage the power of sketching algorithms to provide quick answers with significantly lower energy consumption. In this paper, we propose a novel hardware architecture called EHDSktch -- a set of IP blocks that can be used to implement most of the popular sketching algorithms. We demonstrate an energy savings of 4-10X and a speedup of more than 10X over state-of-the-art software implementations. Leveraging the temporal locality further provides us a performance gain of 3-20% in energy and time and reduces the on-chip memory requirement by at least 50-75%.

In this paper, we present the architecture of the current reuse technique-based inverter stacked-4 amplifier which provide low power consumption and low noise, so as to be used as an analog front end instrumentation cardiac amplifier which decide the overall efficiency of ECG recording system as well as the performance of current reuse technique-based inverter stacked-4 amplifier is also compared with the existing architecture of stacked 2 and stacked 3 amplifier. Based on the comparison result we can conclude that the presented low power architecture of stacked-4 amplifier can be used to gather sensory signal from sensor nodes (electrodes) in IOT-based ECG application. As sensor nodes are generally operated by battery so, the key challenge in the design of IOT-based application is low power consumption.

This paper presents a low power architecture for linear periodically time varying (LPTV) filter by decomposing into finite computational threads. An N-tap, M period LPTV filter architecture is minimized into a single LTI filter by enabling the thread decomposition (TD) of the LPTV filtering operation. The proposed architecture is a generalization to the transposed form structure. A new insight, derived from TD enabled this generalization, which is otherwise not possible. Implementing the LPTV filter with multiplier less functional blocks based on binary common sub-expression elimination (BCSE) algorithm reduced the critical path delay. Experimental results show that the proposed design offers 48.9% reduction in area delay product (ADP) and 14.2% reduction in power delay product (PDP). The LPTV filtering operations in various applications can be realized with the proposed architecture. This work is the first attempt to the ASIC implementation of an efficient architecture for LPTV filter.

The evaluation and optimization methods are presented for energy architecture of distributed electrical propulsion Fuel-cell UAV in this paper. DC power flow model of hybrid power source based on fuel-cell and battery are derived, which is considered with the flighting air dynamics coupling with the multi-propeller powertrain. Based on hybrid power architecture, power flow calculation analysis of the fuelcell DC power system are given, evaluation software for architecture of fuel-cell UAV powertrain is designed, parameterized models of typical powertrain components are build, and multi-objective convex optimization model with some constraints of hybrid power system in the some optimization environment are derived and the optimal solver is performed under different flight stage of UAV in this paper. It is expected to provide optimization and evaluation methods tools for the design and evaluation of distributed electric aircraft. Some preliminary research results are presented in this paper.

With the exponential growth of mobile communications, Small Cell Base Stations (SCBSs) have emerged as an inevitable solution for 5G networks. Nevertheless, due to the significant design challenges associated with providing a reliable energy source for each installation, a wide deployment of SCBSs has not yet happened. In this paper a novel methodology for selecting the optimal power architecture for 5G SCBSs is presented. This approach overcomes the limitations of traditional design strategies by implementing a graph theory-based derivation of the possible configurations. The proposed methodology implements detailed models of the system components, enabling the inclusion of real operating conditions. Multi-objective optimization is selected as the decision-making tool, providing a better understanding of the trade-off between the decision metrics: cost, efficiency, and reliability. Finally, the optimal architecture of a green 5G SCBS in a microgrid-based scenario is obtained.

Advancements in datacenter power architecture has led to 48V to 12V intermediate bus converters becoming a resurgent area of research interested. The 48 volt server architecture, proposed by companies such as Google, can offer significant benefits. This higher voltage reduces the distribution losses by 4x as compared with a 12V distribution, as well ad reducing the power conversion losses at the building level. However, increasing this server rack voltage to 48 volts presents a challenge when converting down to point of load voltages using conventional topologies. The Zero Inductor-Voltage converter that can achieve up to 2.5kW/in3 power density for 70A/12V output. The full load efficiency was measured to be 97.2% with a peak efficiency of 99.1%. This represents the highest efficiency and power density yet demonstrated. The design of the converter is also relatively straightforward as there is no need for active current sharing control, and the converter does not utilize resonant components.

In the present paper a partial power converter is proposed for an electric vehicle fast charging station. The main advantage of this type of converter is that it only processes a reduced percentage of the power consumed by the load. Apart from that, the classical partial power converter architectures presented in the literature require an isolated topology for the stage of conversion. However, in this document a non-isolated topology is applied, specifically, an interleaved single ended primary inductor converter. In addition, in order to observe its benefits, the proposed converter is compared with a conventional full power converter. Finally, it is concluded that the proposed partial power architecture is an attractive solution due to its reduction in the processed power by the converter and its improvement in the efficiency of the application.

This paper proposes a generalized switched function model for a bidirectional DC-DC converters. Typical application for such converters is as a part of an electric vehicle power topology, where different architectures are available when more than one energy source is available. For this reason the model is general enough to incorporate a cascade or a parallel power architecture. The model includes switching and conduction losses of the semiconductor devices and ESR loss of the power inductor. The load of the model is based on the load requirements for a vehicle driving a standard Cycle WLTC.

With the onset of the highly contagious COVID-19 pandemic, early-stage and clinic-independent machine assistance is essential for initial disease diagnosis based on its symptoms such as fever, dry cough, fatigue, and dyspnea. This paper proposes a scalable and low power architecture based on end-to-end Convolutional Neural Networks (CNN) for respiratory-related symptoms (cough and dyspnea) detection. The CNN-based model will be part of the final product running on general computing processors that can assess patients similar to what doctors do at triage and telemedicine using passively recorded audio and other information. The proposed model consists of 1D-convolutions to extract audio features and combinations of 2D-convolutions and fully-connected neurons for classification. The architecture achieves a detection accuracy of 87.5% for cough and 87.3% for dyspnea respectively. The proposed work involves extensive optimization of parameters in order to develop a model architecture that can be implemented on highly constrained power budget devices while maintaining high classification accuracy. This optimization allows us to achieve the model size of 960 KB for cough detection which is 193x smaller than the related works employing the end-to-end CNN architecture. The hardware architecture is designed to provide more versatility in terms of the number of input channels, filters, data width and processing engine (P.E.) in a parameterized manner with the target of proposing a reconfigurable hardware. The proposed architecture is fully synthesized and placed-and-routed on Xilinx Artix-7 FPGA. At 47.6 MHz operating frequency, our cough detection hardware architecture consumes 211 mW of power. On the other hand, dyspnea detection hardware architecture consumes 207 mW power at an operating frequency of 50 MHz. In addition, the proposed hardware architecture meets the latency deadline of 1s needed for the efficient operation of hardware while still being energy-effective compared to related work.

This paper proposes a reconfigurable architecture for residential microgrid (MG). The distinct feature of the residential MG is the power architecture which is developed using Z-source inverter (ZSI) for solar photovoltaic (PV) system and it can be reconfigured to current controlling mode and voltage-frequency controlling mode as well as reactive power controlling mode when solar system is idle. Hence, it improves the utilization factor of solar PV system and contributes to maintain the power quality in distribution feeder, while providing an uninterrupted power supply to the customer. The proposed architecture is developed in four stages. As the first stage, current controlling mode with MPPT is developed in MATLAB/Simulink environment and results are discussed in this paper.

Recently, low power architecture is the major requirement in wireless devices. Cognitive radio is the most significant technology to realize the problem of choosing the temporarily unused channels (Sarijari et al. in EURASIP J Wireless Commun Netw 2015:221, 2015). In this paper, the binomial coefficient (nCk) architecture is proposed for finding the possibilities of detecting the unused spectrum in the cognitive radio network. A novel factorial algorithm is designed using a modified parallel multiplier with Vedic multiplication method (Maharaja in Vedic mathematics, Motilal Banarsidass Publishers Pvt Ltd, Delhi, 2001). Compared to existing factorial algorithm (Saha et al. in Microelectron J 42:1343–1352, 2011), the proposed novel factorial algorithm can perform low power, high speed and occupy less number of logic elements because of the simple data-path reduction method using decoder circuit. A new binomial coefficient architecture is designed using the proposed factorial algorithm. The proposed modules are designed and implemented in Altera Cyclone II FPGA family.

The day by day increase in Electrical Power demand is making the traditional power grid unable to fulfill this intensive need of energy and humans are in a constant search of alternatives to resolve this problem. In this article different power system architectures of South Korea have been discussed by reviewing the smart grids, integration of Micro-girds, the implementation of energy management system in the current power architecture seems the best possible solution. By monitoring all the business goals and to overcome all the basic hurdles, smart grid concept will implement successfully by the end of 2030.

In future active distribution networks (ADNs), microgrids (MGs) may have the possibility to control the power dispatched to the ADN by coordinating the output power of their multiple renewable generation units and energy storage units (ESUs). In this way, each MG may support the active distribution network, while promoting the penetration of renewable energy sources in a rational way. In this paper, we propose a tie-line power flow control of a hybrid MG, including photovoltaic (PV) generator, small wind turbines (WT), and ESUs.Firstly, the structure of the hybrid PV/WT/ESU MG is presented. In this power architecture, the battery is directly connected to the PV side through a DC/DC converter, thus reducing the number of conversions. Secondly, a hierarchical control is proposed to coordinate all those elements of the MG, making the tie-line power flow constant for a period of time, e.g. 15. min. Also, a method to calculate the tie-line power flow to be exchanged between the MG and the ADN is explored, and a power ramp rate is given between different dispatch intervals. Finally, a simulation model of the hybrid MG is built and tested. Simulation results show that the proposed hierarchical control strategy can select the proper operational mode and achieve seamless transfer between different modes. It also presents power curtailment functionality when the difference between the WT/PV output power and tie-line exchanged power flow is too large.

This work presents a modelling framework to enable comparison and trade-off study of different aircraft system architectures. The framework integrates a computational module to select feasible architectures with a modelling platform that simulates the power generation, distribution and fuel consumption of the aircraft as well as system-level models for the system being evaluated. Its capabilities are demonstrated for the case of the electrification of the primary flight control system (PFCS) using different electric technologies (EHA, EMA) and different levels of electrification ranging from the conventional hydraulic to the all-electric. The performances of different architectures are analysed with respect to the change in the mechanical power extracted from the engine, the weight and the fuel burn of the aircraft. The framework demonstrates the capability of evaluating multiple, different, system architectures in a way that is scalable for different systems or different aircraft. It supports a designer evaluating the aircraft-level impact of their design choice at system-level, and it can aid in assessing technology options early in the design process.

In this article, we perform a comprehensive survey of the technical aspects related to the implementation of demand response and smart buildings. Specifically, we discuss various smart loads such as heating, ventilating, and air-conditioning (HVAC) systems and plug-in electric vehicles (PEVs); the power architecture with multibus characteristics; different control algorithms such as the hybrid centralized and decentralized control and the distributed coordination among buildings; the communication technologies and network architectures; and the potential cyber-physical security issues and possible mechanisms for enhancing the system security at both cyber and physical layers. The current status of the demand response in United States, Europe, Japan, and China is reviewed, and the benefits, costs, and challenges of implementing and operating demand response and smart buildings are also discussed.

From the publicity with which it opened the Los Angeles Aqueduct in 1913 to the completion of its new headquarters on Bunker Hill in 1965, the Los Angeles Department of Water and Power (DWP) has employed architecture as advertising for image enhancement and to increase its sale of electricity and water. This study of selected DWP structures, 1924–1965, finds that the message of architectural boosterism can become obsolete before the buildings do. DWP’s architecture presents a complicated legacy and a challenge for the future.

Supercapacitor (SC) assisted low dropout regulator (SCALDO) is a very low-frequency DC-DC converter technique, with high end-to-end efficiency, where the load receives a high slew rate capable low noise output of a linear regulator. This technique can be easily extended with a transformer isolated input stage to achieve the 48-V DC rack power architecture proposed by Google recently. One specific advantage of this new design approach is the two-stage DC-UPS capability by over-sizing the SC bank. In this new SCALDO-derived technique with transformer isolation, by inserting an SC in the input side of the converter, energy transfer towards the load side occurs at a higher frequency, in a combination of forward and flyback modes to reduce the overall volume of the converter. The paper details the magnetics design aspects of the technique providing experimental results of a proof of concept prototype.

The first European Space Power Conference took place in Madrid (Spain) on October 1989, i.e. thirty years before the twelfth, held in Juan-Les-Pins (France). This is a good opportunity to look back at these three decades, which have seen major evolutions in the power systems constituents and, to a lesser extent, architectures. The present paper will first assess the 1989 status, trace these changes through the content of the successive ESPC and try, very cautiously, to sketch a possible, if not foreseeable, future. Are addressed batteries, solar cells and solar generators, power components, converters and systems topologies as well as modelling and testing. Some specific aspects are reviewed in more details when they are either interesting witnesses or precursors of key topics.

The high-efficiency, high-current and low-cost power solutions are required for data centers application, in order to reduce the transmission loss on cables, the high input-voltage dc distribution power architecture has been adopted, the 380-12 V high output current isolated converter is widely used in this application. This paper presents a 300-kHz 1-kW LLC resonant converter using novel integrated transformer and Gallium nitride device that are designed and optimized for the LLC resonant converter. The novel integrated transformer structure is proposed and designed for reducing core-loss, secondary conduction-loss and achieving no gap-loss. In the end, a laboratory prototype is designed and tested. The experimental results have verified the performance of the proposed LLC resonant converter with novel integrated transformer.

The use of DC distribution networks has several advantages, especially for energy saving and integration of energy storage system and renewable energies. In this regard, DC nano-grids are a very interesting solution when distributing electrical power in households. In this paper, an analysis about the possible bidirectional capability of this DC nano-grid is presented. The end-user can freely connect either a passive load (demanding power) or an active one (able to sink current to the grid). The analysis is divided into three different parts. First, a discussion about the most promising power architecture is addressed, taking into consideration the loads in a house. Second, a standard for voltage regulation in a bidirectional DC nano-grid is proposed. Finally, a possible bus provider for this particular bidirectional DC nano-grid is also addressed. This power converter is based on a Dual Active Bridge cascaded with five synchronous buck converters. The key design aspects of the proposed topology are analyzed to emphasize the particular constraints imposed by the standard and the power architecture. A 500 W, 380 V to 24 V bidirectional bus provider has been built in order to experimentally validate the standard proposal and the design aspects.

Energy consumption of HPC centers becomes a major limitation in building a new peta or exascale system. In this paper we evaluate the approach of dynamic application tuning used to reduce energy consumption of HPC systems, introduced in the Horizon 2020 READEX project, on the IBM’s Power8 system. A D.A.V.I.D.E HPC system installed in CINECA has been selected for these experiments due to its advanced power consumption monitoring system, which provides power samples at high sampling rate of 1kHz, that are stored in the internal memory and can be read on request. In order to perform the presented evaluations we have enhanced our in-house C/C++MERIC library to support both hardware parameters tuning on Power8 system as well as energy measurement system of the D.A.V.I.D.E. We have used two hardware parameters that are available to the user on this system: (1) Dynamic Voltage and Frequency Scaling and (2) concurrency throttling with focus on hyperthreading, which plays a significant role with respect to performance on Power8 systems. As a test application we have used the ESPRESO FEM library, which is fully fledged application with several regions that shows different kinds of behavior (compute, memory, I/O or communication bound). Each of the regions may have its optimal configuration of the tuned parameters to utilize the system however at the same time without wasting the resources. In this way we were able to reduce the application runtime about 23.7% when tuning to reduce runtime or 27.3% of energy with 9.9% runtime savings when tuning for minimal energy consumption.

[EN] Central inverters are usually employed in large photovoltaic farms because they offer a good compromise between costs and efficiency. However, inverters based on a single power stage have poor efficiency in the low power range, when the irradiation conditions are low. For that reason, an extended solution has been the parallel connection of several inverter modules that manage a fraction of the full power. Besides other benefits, this power architecture can improve the efficiency of the whole system by connecting or disconnecting the modules depending on the amount of managed power. In this work, a control technique is proposed that maximizes the global efficiency of this kind of systems. The developed algorithm uses a functional model of the inverters¿ efficiency to decide the number of modules on stream. This model takes into account both the power that is instantaneously processed and the maximum power point tracking (MPPT) voltage that is applied to the photovoltaic field. A comparative study of several models of efficiency for photovoltaic inverters is carried out, showing that bidimensional models are the best choice for this kind of systems. The proposed algorithm has been evaluated by considering the real characteristics of commercial inverters, showing that a significant improvement of the global efficiency is obtained at the low power range in the case of sunny days. Moreover, the proposed technique dramatically improves the global efficiency in cloudy days., This work is supported by the Spanish Ministry of Economy and Competitiveness (MINECO), the European Regional Development Fund (ERDF) under Grants ENE2015-64087-C2-2-R and RTI2018-100732-B-C21, and the Spanish Ministry of Education (FPU15/01274).

Sever power supplies and board level voltage regulators are currently the bottleneck limiting efficiency of overall server power architecture efficiency. In order to address this Google has proposed and implemented a 48 volt server architecture that brings a higher voltage level throughout the server rack to reduce distribution losses, and conversion losses upstream of the server power supply. However this change places additional burden on the board-level regulators that must now regulate from 48 volts down to below 1 volt for some components. The most common approach is a two stage approach called the "Intermediate Bus Architecture". A novel topology for an Intermediate Bus Architecture was proposed at APEC 2018. This topology featured extremely high efficiency, very simple control and low component count. However two other critical metrics for a bus converter are scability and power density. The work proposed in this paper demonstrates that the Zero-Inductor Voltage (ZIV) Converter can be easily scaled to multiple phases, and shows a very high density design while maintaining efficiency above other cutting edge solutions. The two-phase prototype achieves up to 800W/in3 power density, 99.2% peak efficiency, and 97.9% full load efficiency for 840W output while maintaining good current sharing across all load conditions. The two-phase prototype requires no additional control, and is highly scalable to different power levels through paralleling.

In order to reduce energy losses in high energy consuming data centers, Google introduced their 48-V rack power architecture in 2016 to replace the previous 12-V DC power distribution line. With the DC voltage increased by 4 times the ohmic losses can be reduced by 16 times. This new architecture is expected to be enhanced with rack-level DC-UPS.Compared to traditional very high-frequency switch mode DC-DC converters with their complexity and interference issues, a typical linear converter generates low-noise high-quality DC, albeit with the very low efficiency. The supercapacitor (SC) assisted low drop-out (SCALDO) regulator is a unique new DC-DC converter that resolves this low-efficiency issue. This paper provides a new design approach to achieve a low-frequency supercapacitor-based energy recovery technique for a 48-V DC power supply with efficiencies comparable to switch mode power supplies but with the added advantage of two-stage DC-UPS capability at no additional cost.

48 V bus converter is widely used in telecom and networks power architecture. This paper presents LLC converter as single stage solution for isolated and regulated bus converter, and addresses the control challenges for this converter. In this paper, Simplified Optimal Trajectory Control (SOTC) is used to control 1 MHz LLC converter with input voltage range 40 V:60 V and frequency range 0.8 MHz: 1.8 MHz. Digital implementation of 2-step SOTC is proposed for the high frequency LLC using a low-speed microcontroller. SOTC can achieve optimum transient response for an LLC operating at resonant frequency but has limited impact at wide gain range. A feedforward compensation is proposed in conjunction with SOTC to achieve optimum transient response at wide input voltage range. Moreover, soft-start-up with adaptive switching frequency is proposed to achieve start-up under limited current stress over the whole input voltage range. Experimental results are demonstrated on a 1 MHz LLC 48 V bus converter using 90MHz TMS320F28069 piccolo MCU.

With its simplicity and the lowest component count incorporating both energy storage and isolation, the flyback converter is an ideal candidate for power levels up to several hundred watts. One inherent drawback of the topology, however, is its poor cross regulation when used in multiple-output applications [1]. Much effort, therefore, has gone into techniques for improving cross regulation [2]. A novel multiplexed approach to the power architecture, where energy packets are steered by a controller to where they are needed, eliminates this drawback and achieves cross regulation within a fraction of 1% while significantly improving system efficiency when compared to conventional post regulation techniques. The new architecture supports multiple outputs driving both constant current and constant voltage loads, enabling the design of a single switch-mode power conversion stage that powers logic circuitry, USB ports, audio channels, and LED strings simultaneously. Examples of working designs along with respective operating characteristics are presented.

The hardware transactional memory (HTM) implementations in commercially available processors are significantly hindered by their tight capacity constraints. In practice, this renders current HTMs unsuitable to many real-world workloads of in-memory databases. This paper proposes SI-HTM, which stretches the capacity bounds of the underlying HTM, thus opening HTM to a much broader class of applications. SI-HTM leverages the HTM implementation of the IBM POWER architecture with a software layer to offer a single-version implementation of Snapshot Isolation. When compared to HTM- and software-based concurrency control alternatives, SI-HTM exhibits improved scalability, achieving speedups of up to 300% relatively to HTM on in-memory database benchmarks.

With the rapid development of “Internet+”, data security issues have penetrated into every industry and business function area today. The implementation of this project will enable China to achieve breakthroughs in the field of data security and master a number of independent core technologies to drive the development of upstream and downstream related industries, significantly improve China’s data security technology, further optimize the structure of China’s information security industry, and prosper the information security market.