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Chip aging that results in small delay defects is one of the possible causes for silent data corruption that has been observed in large datacenters. Chip aging is exacerbated by high software workloads when the chip is deployed in a system. Small delay defects are detected by tests for path delay faults. Path delay faults are typically selected to include the longest testable paths. In addition, functionally possible paths are selected to ensure the detection of small delay defects that can cause a chip to fail during functional operation. To address chip aging, it is suggested in this brief that the longest functionally possible paths through as many lines as possible with the highest susceptibilities to aging should be targeted. A path selection procedure at the gate level is described, that uses the switching activity under functional test sequences to identify functionally possible paths that are the most susceptible to aging. Experimental results for benchmark circuits show that the length of a path and the functional switching activities for lines along the path are independent, and each criterion alone leads to the selection of different paths. The results suggest that both criteria need to be used together for path selection.

VLSI design flows improve design parameters (performance, power, area, and testability) iteratively. Whereas the “shift left” trend implies that changes at the RTL are preferred for improving the design, it is sometimes necessary to make gate-level changes, e.g., because of layout changes or ECO. In an iterative design flow, repeated ATPG to evaluate the testability of a design after design changes have been made creates a bottleneck. The goal of this article is to address this bottleneck considering two-cycle tests for transition faults. The test generation procedure described in third article transforms an LOC test set generated for an earlier version of the design into an LOC test set for a new version without repeating the entire test generation process. To enable the transformation, it is necessary to find a mapping between the inputs and outputs of the earlier and new versions of the design, taking into consideration that RTL resynthesis may produce a new gate-level netlist, with new signal names and different input and output orders. To address two-cycle tests, the mapping is performed over two time frames of the design. Experimental results for industrial circuits with changes made at the RTL as well as gate-level demonstrate significant runtime gains with the test generation procedure described in this article.

The fabrication processes of chips in state-of-the-art technologies may introduce defects of various types, and a large number of tests may be needed for fault detection. However, constraints on the storage requirements of a test set can limit the number of tests and, consequently, the fault coverage. It was shown earlier that reductions in the input storage requirements of a test set can be achieved by using the same stored tests for applying several different tests. One of the operators used for this purpose complements bits of applied tests. The key contributions of this article to this scenario are the following. These issues are considered here for the first time: 1) the use of bit-complemented tests is guided by the fault coverage curve of a complete test set and bit-complementation is applied to tests from the beginning of the fault coverage curve to replace tests at the tail of the curve that detect small numbers of faults; 2) the input and output test data volume are considered together and bit-complementation is used for storing both the tests and their output responses; and 3) the procedure described in this article explores the tradeoff between the storage requirements and the number of applied tests. Experimental results for single-cycle gate-exhaustive faults in benchmark circuits demonstrate the tradeoff.

Distributed test data compression refers to the scenario where each logic block in a design has its own decompression logic and compact set of compressed tests. A static test compaction procedure for this scenario was described recently. The procedure accepts compact compressed test sets for the logic blocks. It combines the test sets into a single shared test set and optimizes it for all the logic blocks. This article describes a dynamic test compaction procedure for the same scenario. The procedure starts from an empty shared test set and considers the logic blocks one by one. It increases the fault coverage of the shared test set either by adding a compressed test or by extending a compressed test already included in the shared test set. Experimental results presented for groups of benchmark circuits demonstrate significant sharing that leads to a significant reduction in the storage requirements for tests.

Iterative synthesis consists of local design modifications to improve design parameters or correct design errors. Incremental test generation was suggested for evaluating the effects of the modifications on the testability of the design. This brief suggests that a fast (incomplete) procedure for identifying undetectable faults is effective in identifying that the testability will deteriorate because of a local design modification without performing test generation. Two experiments are carried out using a procedure that performs successive local design modifications. A modification is accepted only if it does not result in new undetectable faults, and other modifications are eliminated. The results for single stuck-at faults in benchmark circuits demonstrate that fast identification of undetectable faults is typically sufficient for preventing the fault coverage from decreasing because of the modifications.

In the early stages of yield improvement, a faulty unit may produce a large volume of fail data because of the presence of multiple defects in the functional logic. Earlier solutions that address the fail data collection process on the tester make a decision to store fail data for every test separately. This article suggests a more fine-grained approach where fail data is collected for a subset of the tests and outputs. This is represented by storing a partially specified fault-free output response on the tester, and storing a fail data entry for a faulty unit only when it conflicts with a fully specified fault-free output value. Although the fault-free output response is larger, the fail data volume collected for faulty units is reduced. This is important since fail data is collected over many faulty units. This article considers the selection of the partially specified fault-free output response a priori and presents experimental results to demonstrate that the fail data volume is reduced significantly, and accurate logic diagnosis is possible with the reduced fail data.