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Highly entangled quantum states are an ingredient in numerous applications in quantum computing. However, preparing these highly entangled quantum states on currently available quantum computers at high fidelity is limited by ubiquitous errors. Besides improving the underlying technology of a quantum computer, the scale and fidelity of these entangled states in near-term quantum computers can be improved by specialized compilation methods. In this work, the compilation of quantum circuits for the preparation of highly entangled architecture-specific graph states is addressed by defining and solving a formal model. Our model incorporates information about gate cancellations, gate commutations, and accurate gate timing to determine an optimized graph state preparation circuit. Up to now, these aspects have only been considered independently of each other, typically applied to arbitrary quantum circuits. We quantify the quality of a generated state by performing stabilizer measurements and determining its fidelity. We show that our new method reduces the error when preparing a seven-qubit graph state by 3.5x on average compared to the state-of-the-art Qiskit solution. For a linear eight-qubit graph state, the error is reduced by 6.4x on average. The presented results highlight the ability of our approach to prepare higher fidelity or larger-scale graph states on gate-based quantum computing hardware.

Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit design in maximizing the performance and robustness of algorithms on near-term quantum devices. By utilizing eight IBM quantum devices, we analyze how hardware features and algorithm design impact the effectiveness of DD for error mitigation. Our analysis takes into account factors such as circuit fidelity, scheduling duration, and hardware-native gate set. We also examine the influence of algorithmic implementation details, including specific gate decompositions, DD sequences, and optimization levels. The results reveal an inverse relationship between the effectiveness of DD and the inherent performance of the algorithm. Furthermore, we emphasize the importance of gate directionality and circuit symmetry in improving performance. This study offers valuable insights for optimizing DD protocols and circuit designs, highlighting the significance of a holistic approach that leverages both hardware features and algorithm design for the high-quality and reliable execution of near-term quantum algorithms.

System-Level Test (SLT) has been a part of the test flow for integrated circuits for over a decade and still gains importance. However, no systematic approaches exist for test program generation, especially targeting non-functional properties of the Device under Test (DUT). Currently, test engineers manually compose test suites from off-the-shelf software, approximating the end-user environment of the DUT. This is a challenging and tedious task that does not guarantee sufficient control over non-functional properties. This paper proposes Large Language Models (LLMs) to generate test programs. We take a first glance at how pre-trained LLMs perform in test program generation to optimize non-functional properties of the DUT. Therefore, we write a prompt to generate C code snippets that maximize the instructions per cycle of a super-scalar, out-of-order architecture in simulation. Additionally, we apply prompt and hyperparameter optimization to achieve the best possible results without further training., Comment: Testmethoden und Zuverl\"assigkeit von Schaltungen und Systemen, TuZ 2024

Memristors, as emerging nano-devices, offer promising performance and exhibit rich electrical dynamic behavior. Having already found success in applications such as neuromorphic and in-memory computing, researchers are now exploring their potential for cryptographic implementations. In this study, we present a novel power-balanced hiding strategy utilizing memristor groups to conceal power consumption in cryptographic logic circuits. Our approach ensures consistent power costs of all 16 logic gates in Complementary-Resistive-Switching-with-Reading (CRS-R) logic family during writing and reading cycles regardless of Logic Input Variable (LIV) values. By constructing hiding groups, we enable an effective power balance in each gate hiding group. Furthermore, experimental validation of our strategy includes the implementation of a cryptographic construction, xor4SBox, using NOR gates. The circuit construction without the hiding strategy and with the hiding strategy undergo T-test analysis, confirming the significant improvement achieved with our approach. Our work presents a substantial advancement in power-balanced hiding methods, offering enhanced security and efficiency in logic circuits.

This paper presents strategies to improve the performance of digitized counterdiabatic quantum optimization algorithms by cooptimizing gate sequences, algorithm parameters, and qubit mapping. Demonstrations on near-term quantum devices validate the effectiveness of these strategies, leveraging both algorithmic and hardware advantages. Our approach increases the approximation ratio by an average of 4.49$\times$ without error mitigation and 84.8% with error mitigation, while reducing CX gate count and circuit depth by 28.8% and 33.4%, respectively, compared to Qiskit and Tket. These findings provide valuable insights into the codesign of algorithm implementation, tailored to optimize qubit mapping and algorithm parameters, with broader implications for enhancing algorithm performance on near-term quantum devices.

Quantum algorithms implemented on near-term devices require qubit mapping due to noise and limited qubit connectivity. In this paper we propose a strategy called algorithm-oriented qubit mapping (AOQMAP) that aims to bridge the gap between exact and scalable mapping methods by utilizing the inherent structure of algorithms. While exact methods provide optimal solutions, they become intractable for large circuits. Scalable methods, like SWAP networks, offer fast solutions but lack optimality. AOQMAP bridges this gap by leveraging algorithmic features and their association with specific device substructures to achieve optimal and scalable solutions. The proposed strategy follows a two stage approach. First, it maps circuits to subtopologies to meet connectivity constraints. Second, it identifies the optimal qubits for execution using a cost function. Notably, AOQMAP provides both scalable and optimal solutions for variational quantum algorithms with fully connected two qubit interactions on common subtopologies including linear, T-, and H-shaped, minimizing circuit depth. Benchmarking experiments conducted on IBM quantum devices demonstrate significant reductions in gate count and circuit depth compared to Qiskit, Tket, and SWAP network. Specifically, AOQMAP achieves up to an 82% reduction in circuit depth and an average 138% increase in success probability. This scalable and algorithm-specific approach holds the potential to optimize a wider range of quantum algorithms.

A limited number of qubits, high error rates, and limited qubit connectivity are major challenges for effective near-term quantum computations. Quantum circuit partitioning divides a quantum computation into a set of computations that include smaller-scale quantum (sub)circuits and classical postprocessing steps. These quantum subcircuits require fewer qubits, incur a smaller effort for satisfying qubit connectivity requirements, and typically incur less error. Thus, quantum circuit partitioning has the potential to enable quantum computations that would otherwise only be available on more matured hardware. However, partitioning quantum circuits generally incurs an exponential increase in quantum computing runtime by repeatedly executing quantum subcircuits. Previous work results in non-optimal subcircuit executions hereby limiting the scope of quantum circuit partitioning. In this work, we develop an optimal partitioning method based on recent advances in quantum circuit knitting. By considering wire cuts and gate cuts in conjunction with ancilla qubit insertions and classical communication, the developed method can determine a minimal cost quantum circuit partitioning. Compared to previous work, we demonstrate the developed method to reduce the overhead in quantum computing time by 73% on average for 56% of evaluated quantum circuits. Given a one hour runtime budget on a typical near-term quantum computer, the developed method could reduce the qubit requirement of the evaluated quantum circuits by 40% on average. These results highlight the ability of the developed method to extend the computational reach of near-term quantum computers by reducing the qubit requirement at a lower increase in quantum circuit executions.

Near-term quantum computations are limited by high error rates, the scarcity of qubits and low qubit connectivity. Increasing support for mid-circuit measurements and qubit reset in near-term quantum computers enables qubit reuse that may yield quantum computations with fewer qubits and lower errors. In this work, we introduce a formal model for qubit reuse optimization that delivers provably optimal solutions with respect to quantum circuit depth, number of qubits, or number of swap gates for the first time. This is in contrast to related work where qubit reuse is used heuristically or optimally but without consideration of the mapping effort. We further investigate reset errors on near-term quantum computers by performing reset error characterization experiments. Using the hereby obtained reset error characterization and calibration data of a near-term quantum computer, we then determine a qubit assignment that is optimal with respect to a given cost function. We define this cost function to include gate errors and decoherence as well as the individual reset error of each qubit. We found the reset fidelity to be state-dependent and to range, depending on the reset qubit, from 67.5% to 100% in a near-term quantum computer. We demonstrate the applicability of the developed method to a number of quantum circuits and show improvements in the number of qubits and swap gate insertions, estimated success probability, and Hellinger fidelity of the investigated quantum circuits., Comment: to appear in IEEE Quantum Week 2023

Vigorous optimization of quantum gates has led to bipotent quantum architectures, where the optimized gates are available for some qubits but not for others. However, such gate-level improvements limit the application of user-side pulse-level optimizations, which have proven effective for quantum circuits with a high level of regularity, such as the ansatz circuit of the Quantum Approximate Optimization Algorithm (QAOA). In this paper, we investigate the trade-off between hardware-level and algorithm-level improvements on bipotent quantum architectures. Our results for various QAOA instances on two quantum computers offered by IBM indicate that the benefits of pulse-level optimizations currently outweigh the improvements due to vigorously optimized monolithic gates. Furthermore, our data indicate that the fidelity of circuit primitives is not always the best indicator for the overall algorithm performance; also their gate type and schedule duration should be taken into account. This effect is particularly pronounced for QAOA on dense portfolio optimization problems, since their transpilation requires many SWAP gates, for which efficient pulse-level optimization exists. Our findings provide practical guidance on optimal qubit selection on bipotent quantum architectures and suggest the need for improvements of those architectures, ultimately making pulse-level optimization available for all gate types.

First quantum computers very recently have demonstrated "quantum supremacy" or "quantum advantage": Executing a computation that would have been impossible on a classical machine. Today's quantum computers follow the NISQ paradigm: They exhibit error rates that are much higher than in conventional electronics and have insufficient quantum resources to support powerful error correction protocols. This raises questions which relevant computations are within the reach of NISQ architectures. Several "NISQ-era algorithms" are assumed to match the specifics of such computers; for instance, variational optimisers are based on intertwining relatively short quantum and classical computations, thus maximizing the chances of success. This paper will critically assess the promise and challenge of NISQ computing. What has this field achieved so far, what are we likely to achieve soon, where do we have to be skeptical and wait for the advent of larger-scale fully error-corrected architectures?

While scalable, fully error corrected quantum computing is years or even decades away, there is considerable interest in noisy intermediate-scale quantum computing (NISQ). In this paper, we introduce the ArsoNISQ framework that determines the tolerable error rate of a given quantum algorithm computation, i.e. quantum circuits, and the success probability of the computation given a success criterion and a NISQ computer. ArsoNISQ is based on simulations of quantum circuits subject to errors according to the Pauli error model. ArsoNISQ was evaluated on a set of quantum algorithms that can incur a quantum speedup or are otherwise relevant to NISQ computing. Despite optimistic expectations in recent literature, we did not observe quantum algorithms with intrinsic robustness, i.e. algorithms that tolerate one error on average, in this evaluation. The evaluation demonstrated, however, that the quantum circuit size sets an upper bound for its tolerable error rate and quantified the difference in tolerate error rates for quantum circuits of similar sizes. Thus, the framework can assist quantum algorithm developers in improving their implementation and selecting a suitable NISQ computing platform. Extrapolating the results into the quantum advantage regime suggests that the error rate of larger quantum computers must decrease substantially or active quantum error correction will need to be deployed for most of the evaluated algorithms.

Variational quantum algorithms have been one of the most intensively studied applications for near-term quantum computing applications. The noisy intermediate-scale quantum (NISQ) regime, where small enough algorithms can be run successfully on noisy quantum computers expected during the next 5 years, is driving both a large amount of research work and a significant amount of private sector funding. Therefore, it is important to understand whether variational algorithms are effective at successfully converging to the correct answer in presence of noise. We perform a comprehensive study of the variational quantum eigensolver (VQE) and its individual quantum subroutines. Building on asymptotic bounds, we show through explicit simulation that the VQE algorithm effectively collapses already when single errors occur during a quantum processing call. We discuss the significant implications of this result in the context of being able to run any variational type algorithm without resource expensive error correction protocols.

The reliable, deterministic production of trustworthy high-quality single photons is a critical component of discrete variable, optical quantum technology. For single-photon based fully error-corrected quantum computing systems, it is estimated that photon sources will be required to produce a reliable stream of photons at rates exceeding 1 GHz [1]. Photon multiplexing, where low probability sources are combined with switching networks to route successful production events to an output, are a potential solution but requires extremely fast single photon switching with ultra-low loss rates. In this paper we examine the specific properties of the switching elements and present a new design that exploits the general one-way properties of common switching elements such as thermal pads. By introducing multiple switches to a basic, temporal multiplexing device, we are able to use slow switching elements in a multiplexed source being pumped at much faster rates. We model this design under multiple error channels and show that anticipated performance is now limited by the intrinsic loss rate of the optical waveguides within integrated photonic chipsets.

With the advent of the Internet of Things, nanoelectronic devices or memristors have been the subject of significant interest for use as new hardware security primitives. Among the several available memristors, BiFe$\rm O_{3}$ (BFO)-based electroforming-free memristors have attracted considerable attention due to their excellent properties, such as long retention time, self-rectification, intrinsic stochasticity, and fast switching. They have been actively investigated for use in physical unclonable function (PUF) key storage modules, artificial synapses in neural networks, nonvolatile resistive switches, and reconfigurable logic applications. In this work, we present a physics-inspired 1D compact model of a BFO memristor to understand its implementation for such applications (mainly PUFs) and perform circuit simulations. The resistive switching based on electric field-driven vacancy migration and intrinsic stochastic behaviour of the BFO memristor are modelled using the cloud-in-a-cell scheme. The experimental current-voltage characteristics of the BFO memristor are successfully reproduced. The response of the BFO memristor to changes in electrical properties, environmental properties (such as temperature) and stress are analyzed and consistent with experimental results., Comment: 13 pages and 8 figures

We present a detailed study of portfolio optimization using different versions of the quantum approximate optimization algorithm (QAOA). For a given list of assets, the portfolio optimization problem is formulated as quadratic binary optimization constrained on the number of assets contained in the portfolio. QAOA has been suggested as a possible candidate for solving this problem (and similar combinatorial optimization problems) more efficiently than classical computers in the case of a sufficiently large number of assets. However, the practical implementation of this algorithm requires a careful consideration of several technical issues, not all of which are discussed in the present literature. The present article intends to fill this gap and thereby provide the reader with a useful guide for applying QAOA to the portfolio optimization problem (and similar problems). In particular, we will discuss several possible choices of the variational form and of different classical algorithms for finding the corresponding optimized parameters. Viewing at the application of QAOA on error-prone NISQ hardware, we also analyze the influence of statistical sampling errors (due to a finite number of shots) and gate and readout errors (due to imperfect quantum hardware). Finally, we define a criterion for distinguishing between "easy" and "hard" instances of the portfolio optimization problem, Comment: 28 pages, 8 figures

Today's Noisy Intermediate-Scale Quantum (NISQ) computers support only limited sets of available quantum gates and restricted connectivity. Therefore, quantum algorithms must be transpiled in order to become executable on a given NISQ computer; transpilation is a complex and computationally heavy process. Moreover, NISQ computers are affected by noise that changes over time, and periodic calibration provides relevant error rates that should be considered during transpilation. Variational algorithms, which form one main class of computations on NISQ platforms, produce a number of similar yet not identical quantum ``ansatz'' circuits. In this work, we present a transpilation methodology optimized for variational algorithms under potentially changing error rates. We divide transpilation into three steps: (1) noise-unaware and computationally heavy pre-transpilation; (2) fast noise-aware matching; and (3) fast decomposition followed by heuristic optimization. For a complete run of a variational algorithm under constant error rates, only step (3) needs to be executed for each new ansatz circuit. Step (2) is required only if the error rates reported by calibration have changed significantly since the beginning of the computation. The most expensive Step (1) is executed only once for the whole run. This distribution is helpful for incremental, calibration-aware transpilation when the variational algorithm adapts its own execution to changing error rates. Experimental results on IBM's quantum computer show the low latency and robust results obtained by calibration-aware transpilation., Comment: Accepted by QCE22 (2022 IEEE International Conference on Quantum Computing & Engineering (QCE))

Quantum algorithms promise quadratic or exponential speedups for applications in cryptography, chemistry and material sciences. The topologies of today's quantum computers offer limited connectivity, leading to significant overheads for implementing such quantum algorithms. One-dimensional topology displacements that remedy these limits have been recently demonstrated for architectures based on Rydberg atoms, and they are possible in principle in photonic and ion trap architectures. We present the first optimal quantum circuit-to-architecture mapping algorithm that exploits such one-dimensional topology displacements. We benchmark our method on quantum circuits with up to 15 qubits and investigate the improvements compared with conventional mapping based on inserting swap gates into the quantum circuits. Depending on underlying technology parameters, our approach can decrease the quantum circuit depth by up to 58% and increase the fidelity by up to 29%. We also study runtime and fidelity requirements on one-dimensional displacements and swap gates to derive conditions under which one-dimensional topology displacements provide benefits., Comment: to appear in ICCAD'21

System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering., Comment: 7 pages, 2 figures

Modern electronic systems become evermore complex, yet remain modular, with integrated circuits (ICs) acting as versatile hardware components at their heart. Electronic design automation (EDA) for ICs has focused traditionally on power, performance, and area. However, given the rise of hardware-centric security threats, we believe that EDA must also adopt related notions like secure by design and secure composition of hardware. Despite various promising studies, we argue that some aspects still require more efforts, for example: effective means for compilation of assumptions and constraints for security schemes, all the way from the system level down to the "bare metal"; modeling, evaluation, and consideration of security-relevant metrics; or automated and holistic synthesis of various countermeasures, without inducing negative cross-effects. In this paper, we first introduce hardware security for the EDA community. Next we review prior (academic) art for EDA-driven security evaluation and implementation of countermeasures. We then discuss strategies and challenges for advancing research and development toward secure composition of circuits and systems., Comment: To appear in DATE'20

We present a quantum circuit representation consisting entirely of qubit initialisations (I), a network of controlled-NOT gates (C) and measurements with respect to different bases (M). The ICM representation is useful for optimisation of quantum circuits that include teleportation, which is required for fault-tolerant, error corrected quantum computation. The non-deterministic nature of teleportation necessitates the conditional introduction of corrective quantum gates and additional ancillae during circuit execution. Therefore, the standard optimisation objectives, gate count and number of wires, are not well-defined for general teleportation-based circuits. The transformation of a circuit into the ICM representation provides a canonical form for an exact fault-tolerant, error corrected circuit needed for optimisation prior to the final implementation in a realistic hardware model., Comment: Shorter Computer Science focused version of arXiv:1509.02004

Fault-tolerant quantum error correction is a necessity for any quantum architecture destined to tackle interesting, large-scale problems. Its theoretical formalism has been well founded for nearly two decades. However, we still do not have an appropriate compiler to produce a fault-tolerant, error corrected description from a higher level quantum circuit for state of the art hardware models. There are many technical hurdles, including dynamic circuit constructions that occur when constructing fault-tolerant circuits with commonly used error correcting codes. We introduce a package that converts high level quantum circuits consisting of commonly used gates into a form employing all decompositions and ancillary protocols needed for fault-tolerant error correction. We call this form the (I)initialisation, (C)NOT, (M)measurement form (ICM) and consists of an initialisation layer of qubits into one of four distinct states, a massive, deterministic array of CNOT operations and a series of time ordered $X$- or $Z$-basis measurements. The form allows a more flexbile approach towards circuit optimisation. At the same time, the package outputs a standard circuit or a canonical geometric description which is a necessity for operating current state-of-the-art hardware architectures using topological quantum codes., Comment: 17 pages, 17 figures, comments welcome. The compiler source code is released under the Microsoft Reference Source License (Ms-RSL, http://referencesource.microsoft.com/ license.html) at http://www.teqcnique.com/icmconvert

Quantum computing promises a new approach to solving difficult computational problems, and the quest of building a quantum computer has started. While the first attempts on construction were succesful, scalability has never been achieved, due to the inherent fragile nature of the quantum bits (qubits). From the multitude of approaches to achieve scalability topological quantum computing (TQC) is the most promising one, by being based on an flexible approach to error-correction and making use of the straightforward measurement-based computing technique. TQC circuits are defined within a large, uniform, 3-dimensional lattice of physical qubits produced by the hardware and the physical volume of this lattice directly relates to the resources required for computation. Circuit optimization may result in non-intuitive mismatches between circuit specification and implementation. In this paper we introduce the first method for cross-level validation of TQC circuits. The specification of the circuit is expressed based on the stabilizer formalism, and the stabilizer table is checked by mapping the topology on the physical qubit level, followed by quantum circuit simulation. Simulation results show that cross-level validation of error-corrected circuits is feasible., Comment: 12 Pages, 5 Figures. Comments Welcome. RC2014, Springer Lecture Notes on Computer Science (LNCS) 8507, pp. 189-200. Springer International Publishing, Switzerland (2014), Y. Shigeru and M.Shin-ichi (Eds.)

Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit., Comment: 16 Pages, 8 Figures, to Appear Sci. Rep

The realisation of large-scale quantum computing is no longer simply a hardware question. The rapid development of quantum technology has resulted in dozens of control and programming problems that should be directed towards the classical computer science and engineering community. One such problem is known as Pauli tracking. Methods for implementing quantum algorithms that are compatible with crucial error correction technology utilise extensive quantum teleportation protocols. These protocols are intrinsically probabilistic and result in correction operators that occur as byproducts of teleportation. These byproduct operators do not need to be corrected in the quantum hardware itself. Instead, byproduct operators are tracked through the circuit and output results reinterpreted. This tracking is routinely ignored in quantum information as it is assumed that tracking algorithms will eventually be developed. In this work we help fill this gap and present an algorithm for tracking byproduct operators through a quantum computation. We formulate this work based on quantum gate sets that are compatible with all major forms of quantum error correction and demonstrate the completeness of the algorithm., Comment: 5 Pages, 1 figure, Accepted for Design, Automation and Test In Europe (DATE'2014)

Topological quantum computing has recently proven itself to be a very powerful model when considering large- scale, fully error corrected quantum architectures. In addition to its robust nature under hardware errors, it is a software driven method of error corrected computation, with the hardware responsible for only creating a generic quantum resource (the topological lattice). Computation in this scheme is achieved by the geometric manipulation of holes (defects) within the lattice. Interactions between logical qubits (quantum gate operations) are implemented by using particular arrangements of the defects, such as braids and junctions. We demonstrate that junction-based topological quantum gates allow highly regular and structured implementation of large CNOT (controlled-not) gate networks, which ultimately form the basis of the error corrected primitives that must be used for an error corrected algorithm. We present a number of heuristics to optimise the area of the resulting structures and therefore the number of the required hardware resources., Comment: 7 Pages, 10 Figures, 1 Table

We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In contrast to existing code-based methods, we allow unspecified values in matching vectors, which allows encoding of arbitrary test sets using a relatively small number of code-words. Experimental results for both stuck-at and path delay fault test sets for ISCAS circuits demonstrate an improvement compared to existing techniques., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)