Search

Impedance-source inverters with coupled inductors can provide much higher voltage gains, but occasionally at the expense of discontinuous input currents and large voltage spikes at their dc-links. The former is caused by absence of inductances at their inputs, while the latter is due to unintentional interruptions of leakage currents through their coupled inductors. These problems have now been solved here by a new family of dual-winding impedance-source inverters (DW-ISIs). Each DW-ISI can recycle leakage energy from its two windings to a few clamping capacitors, which in turn help to prevent voltage spikes. This, together with the presence of an inductance for smoothing its input current, renders the family of DW-ISIs to be highly effective, while not compromising voltage and current stresses when compared to other precedent inverters. In addition, to simplify the circuit analysis, a reactive component elimination method has been proposed in this paper. Simulation and experimental results have confirmed the validity of the proposed topologies.

Reliable and affordable AC/AC power conversion plays a key role in supplying various electrical equipment. Among the options available, direct matrix converter (DMC) outperforms its counterparts (e.g. AC/DC/AC), in terms of lifespan and compactness, due to its omission of fragile and bulky dc-link capacitors. However, most off-the-shelf DMC modules suffer from high input current spikes, which if unresolved, can noticeably increase current stresses and lower efficiency. Origin of the spikes and a mechanism for reducing them are hence studied in the paper, before developing a low-cost SiC-Si hybrid module for implementing DMC reliably and compactly. The developed module consists of 18 Si insulated gate bipolar transistors (IGBTs) and 18 SiC junction barrier Schottky (JBS) diodes connected in a common-collector structure. The improved reverse recovery property of the SiC JBS diodes then permits the hybrid module to operate with mitigated current spikes. To demonstrate, the hybrid module has been fabricated, tested and compared with two counterparts in terms of their input current spikes and power losses over different output voltages and switching frequencies. Experimental results have proven the expected performances of the hybrid DMC module, which collectively, can accelerate large-scale emergence of small all-semiconductor drives for industrial pumps, cooling and refrigeration systems, and others widely needed in developing economies.

Voltage boosting three-level inverters may present a monotonically increasing or decreasing voltage gain when enlarging the pulse-width modulation (PWM) ratio. To produce a flexible voltage gain, this paper proposes a novel three-phase three-level PWM inverter by cascading a traditional two-level three-leg (B6) inverter with half-bridges. The proposed inverter is supplied by an inductive dc-link consisting of a dc source in series with an inductor that is charged by shooting through the half-bridges in the B6 structure. The voltages across the cascaded half-bridges are subsequently boosted, and the output voltage is stepped up due to the cascaded connection. A moderate voltage gain is achieved with proper selections of two modulation variables while maximizing the PWM ratio. In particular, when the two modulation variables are equal, a constant voltage boosting gain of two is maintained irrespective of the PWM ratio. Additionally, low voltages are induced on the components, which facilitates the use of low-voltage devices. The operating principle of the proposed inverter with a modified third-harmonic-injection (THI) PWM scheme is presented, followed with theoretical analysis, comparison, and design considerations. Experimental tests on a 1.5-kVA inverter prototype verify its feasibility.

Switched-capacitor-based multilevel inverters for boost-type dc–ac power conversions usually exhibit a trade-off between the switch count and switch-voltage rating, i.e., a reduction of one necessitating an increase of the other. Such a dilemma is well addressed in this article by proposing a novel single-phase nine-level inverter based on a switched-capacitor network with a single switch. The proposed inverter then reduces the number of switches while generating a boosted dc-link voltage. A unique six-switch full-bridge cooperating with a low-frequency half-bridge further steps-up the output voltage with a quadruple gain. The voltage stresses on the power devices are, however, maintained low even under the boosted high output voltage, as all the switches/diodes can be clamped to any of the low-voltage capacitors. Consequently, low-voltage power devices can be utilized, reducing the overall power loss. Detailed theoretical analysis, calculations, and design considerations of the proposed inverter are provided. Comparisons with the prior-art inverters illustrate its advantages. Simulations and experimental tests on a 1-kVA inverter prototype verify the above-claimed benefits.

A three-phase three-level converter with an LCL filter has been used in the industry because of its low switching harmonics. However, it inevitably suffers from dc neutral-point imbalance, which may unnecessarily stress semiconductors and deteriorate power quality. The imbalance will, nevertheless, naturally rebalance, but it usually takes a long time. A common rectification is, thus, to add an active or a passive booster to speed up the balancing. An active booster requires sensitive sensors and control modification, which will increase the system cost and complexity. A passive booster is, therefore, preferred owing to its exemption of monitoring and control efforts. The existing three-phase passive booster, however, contains several extra separate LC components, which are normally not functioning during the balanced conditions. They should, hence, be reduced. One approach is to dual use the existing LCL (or other high-order) filter for both harmonic filtering and dc-link balancing. Topologically, it requires only the addition of one extra capacitor along the return common-mode path. Using newly formulated criterions related to sizing, harmonic, and modulation selections, the balancing performance of the resulting capacitive balancer has been evaluated comprehensively. Finally, an experimental prototype is built for testing the balancing mechanism under different operating conditions.

Modulation schemes play a key role in effectively driving the current source converter (CSC). Among various modulation schemes, the carrier-based pulse width modulation (CB-PWM) has gained much attention owing to its inherent auto-sequencing process. However, the fixed switching patterns in the existing CB-PWM methods reduce the available degrees of freedom, which imposes underlying restrictions on the performance of a CSC (e.g., to minimize the switching frequency or to reduce the current ripple). To address this issue, an innovative concept of two-stage modulation, which modulates the active and zero current vectors in a switching sequence, respectively, in two stages, is explored in this article. Based on that, this article proposes a generic CB-PWM scheme with adjustable switching patterns for flexibly modulating the CSC. Its mechanism is presented to develop its modulation characteristics. It shows that the proposed PWM scheme can flexibly achieve different modulation objectives by only adjusting the offset voltage in the second stage. Three derivations of the proposed scheme have then been discussed in detail, which can achieve a minimized switching frequency, a reduced dc-link current ripple, or a compromise between them. Representative experimental results have been provided to verify the effectiveness of the proposed modulation scheme.

Microinverters for photovoltaic (PV) energy conversion typically encounter challenges, including the requirement of a voltage boost and suppression of the high-frequency leakage current. These challenges are usually not met simultaneously if only a standard full ( H )-bridge is used. Such limitation is, however, not applicable to the proposed dual-boost H -bridge inverter, which uses only four switches and a unique dual-boost circuit for voltage boosting and forming a common ground. The latter stops PV terminal voltages from changing rapidly, and hence, no high-frequency capacitive current leaking to the ground even without using extra switches. Additionally, the proposed inverter can operate with either one or two PV sources whose terminal voltages need not be balanced. One of the source voltages can, in fact, fall to zero (due to shading) without affecting the continuous operation of the inverter, whose modulation has been formulated to keep its conduction losses low at a steady dc-link voltage. The dc-link capacitor across the H -bridge meanwhile decouples the pulsating output power, which in practice, has always challenged the design of single-phase microinverters. These intended performances have eventually been proven by the simulation and experimental results of a 500-W prototype.

Single-phase symmetrical five-level converter offers a low-harmonic power interface, whose attractiveness is nevertheless affected by dc-link voltage imbalance. Fast rebalancing methods have therefore been proposed, if the natural balancing speed of the converter is intolerable. One possible method is to add a separate parallel RLC branch between the converter and its filter. Being parallel, the branch does not change spectral properties of the converter and filtering properties of the filter, in addition to its robust sensor-less requirement. However, being separated, it does not properly integrate with the filter to explore dual usabilities of the components. This article therefore proposes a few differential-mode (DM) filters with each having a common-mode (CM) capacitor as the balancing accelerator. The accelerator does not conduct and hence consume no power during the normal balanced condition. It conducts only when an imbalance occurs and directs only those harmonics with fast balancing ability to the dc link. Its design is simple and can conveniently be performed with an appropriate CM harmonic model. Its performance has ultimately been verified by simulation and experimental results obtained with two different modulation schemes.

The performance of a current source converter (CSC) is greatly affected by its adopted modulation schemes. Among various modulation schemes, the carrier-based pulsewidth modulation (CB-PWM) has gained increasing attention owing to its inherent autosequencing process. However, existing CB-PWM schemes suffer from either high switching harmonics in ac current or high low-order common-mode voltage (CMV), and sometimes, both, which restrains the application of this promising scheme. To address this issue, this article explores the modulation mechanism of CB-PWM for a CSC. Based on that, this article proposes a direct CB-PWM scheme. Its implementation, mechanism, and characteristics have been developed and presented in detail. It is shown that the proposed scheme enjoys inherent low switching frequency, easy implementation, as well as high dc current utilization. More importantly, compared with existing CB-PWMs, the proposed scheme can simultaneously reduce the switching harmonics of ac current and the low-order CMV for a CSC. These superior performances can bring potential benefits to scale down the ac filter and common-mode choke for practical CSC applications. Effectiveness of the proposed scheme is verified experimentally with a CSC operating as an inverter.

Split-source inverter (SSI) has been proved to be an attractive single-stage dc/ac converter for its compact structure, continuous input voltage, and input current. However, due to the coupling of the boost stage and the inverter stage, SSI suffers from the low dc-link voltage utilization problem, which will increase the system cost and switching losses. To break through this inherent limitation, this article proposes an active SSI (ASSI). It replaces the two clamping diodes in SSI with reverse-blocking switches, which features extended control degrees of freedom. One modulation scheme tailored for the ASSI has also been developed in this article to enhance its performance. Theoretical analyses and simulation results show that the proposed ASSI features not only a high dc-link voltage utilization ratio but also higher efficiency compared to the traditional SSI. Finally, the effectiveness of the proposed ASSI has been verified experimentally.

Small-signal stability of three-phase grid-connected converters can be analysed by using the impedance-based method in d-q frame. Based on this approach, the d-q impedance models of both source and load subsystems are represented with 2-by-2 matrices, and their ratio (known as the return ratio matrix) is used for stability assessment. This, however, requires to apply the generalized Nyquist criterion (GNC), due to the intrinsic multi-input multi-output (MIMO) property of the d-q system. During the process, some complexities are inevitably caused because of the need to calculate the ratio of the impedance matrices, and to obtain the eigenvalues of the return ratio matrix. In this context, this paper presents an equivalent single-input single-output (SISO) model for the d-q impedance of three-phase grid-connected converters, which leads to two scalar impedance ratios of d- and q-axis, instead of the conventional 2-by-2 return ratio matrix. Consequently, the stability of the two SISO systems can be analysed by using the classic Nyquist stability criterion (NC), resulting in a much simpler and more intuitive analysis process than GNC. The equivalence between the original MIMO d-q impedance model and the proposed SISO model in stability assessment is verified by comparing their stability conditions. As an example of applying this approach, the effects of PLL, grid impedance, and power control on a grid-connected converter are investigated. The performed analysis is finally validated by Matlab/Simulink simulations.

A three-winding coupled inductor connected as a Y-shaped impedance network has been used in dc–dc and dc–ac converters for producing a high voltage gain for renewable applications. Its versatility is further extended in this article by the proposed differential Y-source inverter with two Y-source networks. The proposed inverter is modulated by a half-sine wave, which permits only one coupled inductor and two power switches of a phase-leg to operate at a high switching frequency during each half-fundamental cycle. The outcome is significantly reduced switching losses for its semiconductors. As for leakage inductances due to imperfect coupling, their effects have been minimized by two lossless diodes, included to prevent abrupt dissipation of leakage energy. Instead, the leakage energy discharges and then recycles to the dc-link capacitors, which, in turn, help to clamp voltages across the power switches. Detailed analyses of the inverter are given in this article, supported by simulation and experimental results obtained with a 250-W prototype for boosting a 30-V dc input to a 110-V ac output.

Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has a smaller short-circuit tolerance, and hence requires faster and more accurate short-circuit protection. One prospective method is to combine fast di/dt detection with an integration circuit. The former is for detecting the extremely fast increase of short-circuit current, while the latter is for generating a scaled copy of the short-circuit current for comparison with a threshold. The integration is almost always performed with a resistive-capacitive (RC) low-pass filter due to its simplicity. However, it does not produce consistent results under different load and fault conditions, which can, in turn, cause the detection to fail. An alternative di/dt-RCD (RC + diode) protective circuit has therefore been proposed to offer more accurate and consistent results, irrespective of the fault types. Design equations for the circuit have been derived for implementing an experimental setup, from which results have proven the effectiveness of the proposed di/dt-RCD protection.

Coupled-inductor-based impedance-source inverters have been suggested as a solution for improving the voltage boost capability. However, large voltage spikes can sometimes appear across the switch bridge if the leakage inductance of the coupled inductor cannot be nullified. Higher voltage-rated switches are, therefore, necessary for implementing each inverter with generally lower efficiency anticipated. To solve the above issues, this article proposes a high-efficiency T-source inverter (HE-TSI) with leakage energy recycled through several passive elements and, hence, avoided voltage spikes across the switch bridge. To reveal the prominent characteristics of the HE-TSI, it has been compared with the traditional T-source inverter in the terms of extents of voltage spikes across the switch bridge, voltage stresses, current stresses, and efficiency. The simulation and experimental results have verified the validity of the proposed HE-TSI.

Starting from a common principle, two new coupled-inductor-based dc–dc converters with large dc gains are proposed. Both of them present a low voltage stress on the power switch with their leakage inductance energy recuperated to the load. The first coupled-inductor-based converter employs two diode–capacitor voltage multipliers (VMs) inserted in an innovative way to give it many advantages. Specifically, the first VM is placed near the switch to serve as both a multiplier and a switch-voltage clamp cell, while the second one is inserted into the output circuit. The two VMs working in harmony then provide a very large dc gain. The conduction losses are also reduced as power switches with low ON-state resistance can be selected due to the clamping role of the first VM. Moreover, the availability of capacitors of both VMs in the output diode loop results in low voltage stress on all semiconductor devices. The choice of a lower voltage-rating output diode with a lower parasitic capacitance can then alleviate oscillations between the leakage inductance and diode capacitance at its turn-off. The second converter uses a three-winding coupled inductor and a single VM, forming a new hybrid VM cell. Its component count is reduced without affecting the practical dc gain. Its advantage is the elimination of the output diode recovery problem and thus does not result in spikes at its turn-off. Operational principles and dc steady-state analyses of the two converters are discussed, followed by comparison with available converters. The experimental results from two prototypes built for supplying a 400-V grid are given for validating the feasibility and theoretical analyses of the proposed converters.

Split-source inverter (SSI) is a topology developed for flexibly stepping up and down its ac output voltage using only a standard inverter bridge. However, when configured as a single-phase inverter, it is still burdened by common second-order ripples. This study, therefore, proposes a modified SSI (MSSI) that can perform dual power decoupling. Unlike existing schemes, dual power decoupling makes use of both dc- and ac-side capacitors for diverting second-order ripples away from the dc source, which may be solar or other types of sources that do not work well with sizable ripples. Dual power decoupling, however, requires careful topological changes, before its effective realisation can be achieved with only a standard inverter bridge and a very small overall capacitance. Design of this capacitance and its comparison with passive decoupling have then been analysed, before testing the MSSI in experiments. Results obtained have verified the MSSI as an enhanced single-phase inverter with both buck and boost abilities while using no extra switches.

A three-winding coupled inductor, arranged as a Y -source network, has been used for voltage boosting with a standard inverter bridge and no other active switches. However, its maximum modulation and boost duty ratios are correlated with an increase of one maximum necessitating the reduction of the other. Its voltage quality and dc-bus utilization will hence deteriorate greatly at high gain. Moreover, in the presence of nonnegligible leakage, the Y- source network experiences large voltage spikes caused by unintentionally abrupt inductive current changes. Its coupling coefficient must hence be very close to unity or a snubber and always be added. To overcome these limitations, a split- Y- source inverter has been proposed, whose maximum modulation and boost duty ratios can be increased simultaneously, while using only a single-inverter bridge. It is also not burdened by inrush currents and voltage spikes and hence does not impose strict requirements on coupling and snubber. These advantages are in addition to the increased freedom of tuning two turns ratios to keep the total number of turns small, while retaining a high-voltage boost. Theoretical analyses, simulations, and experimental results have successfully verified the performance of the proposed inverter.

In a three-phase three-level grid-connected inverter, the ac output current ripple actually fluctuates four times per switching period with each fluctuation generating some core loss. However, only the two larger fluctuations are considered in most loss estimation methods, resulting in a smaller core loss evaluation. In this letter, an alternative method has, hence, been proposed, beginning with the deduction of fundamental and ripple equivalent circuits from the inverter. These circuits permit current ripple to be calculated, from which its four fluctuations are all considered for forming the dual current-ripple envelopes (DCREs). These DCREs, together with the fundamental current and a selected core loss model, can then be solved to give the estimated fundamental and ripple core loss values. The nonlinear characteristic of the filter inductor has also been considered in the calculation of the DCREs and the core loss. The estimated values have eventually been verified through testing with a 10-kW three-phase T-type three-level grid-connected inverter.

Most grid-connected inverters can operate in both grid-connected and islanded modes with usually different control schemes adopted in each mode. The control schemes, if noticeably complex and different, can result in inrush currents and voltage distortions at instants of mode transfer. An existing grid-connected form of droop control has hence been developed from the usual islanded droop control to better streamline the transfer. However, the grid-connected droop control does not regulate the grid current directly, causing it to distort by grid voltage harmonics and respond slower during a transient. The motivation here is thus to propose another highly unified droop control scheme that can regulate the grid current directly with a transfer dynamic lasting only two fundamental cycles. This is in addition to the usual targets of seamless transfer and proper power sharing among the islanded inverters. The hypothetical approach followed is to reformulate the grid-connected and islanded control schemes, so that mode transfer can simply be treated as a normal change of voltage reference, rather than an inner change of control structure. The final unified scheme has been tested in simulation and experiments with results apparently confirming its precise grid-current regulation, islanded voltage regulation and seamless mode transfer within two fundamental cycles.