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This article shows both theoretical and experimental analyses of a fully integrated CMOS active gate driver (AGD) developed to control the high d v /d t of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the d v /d t with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the d v /d t sequence of the switching transients. Hence, the d v /d t and d i /d t can be actively controlled separately, and the tradeoff between the d v /d t and E ON switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for d v /d t active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak d v /d t from –175 to –120 V/ns for the 400 V application.

International audience; Dans cet article, nous présentons une technique de contrôle actif de grille pour maitriser la vitesse de commutation de transistors de puissance à semi-conducteur grand-gap. Un circuit de commande rapprochée innovant, permet de ralentir la vitesse de commutation à l'amorçage du transistor de puissance, réduisant ainsi les perturbations CEM, sans pour autant impacter trop lourdement les pertes de commutation. La méthode proposée est implémentée dans deux circuits intégrés en technologie CMOS qui permettent d'obtenir des temps de réaction pour une boucle de rétroaction inférieurs à la nanoseconde. Avec de telles performances, il est montré expérimentalement qu'il est possible de contrôler des vitesses de commutation supérieures à 100 V/ns sous des tensions de 400 V.

International audience; The objective of this work is to show the intrinsic limitations of a CMOS technology for the realization of an Active Gate Driver (AGD) with active dv/dt control loop. Due to a theoretical study using first order models of CMOS submicron transistors, the main equations providing the link between feedback loop bandwidth and specific technology parameters are obtained. This optimization study allows us to determine the theoretical limits in terms of bandwidth and silicon area. Then, it becomes possible to determine the most appropriate switching control method to implement depending on the application requirements (high efficiency, low EMI), i.e. active feedback with adjustable gain, while ensuring suitable time delays. A feedback loop bandwidth of 1.59 GHz using an 1pF integrated capacitor to address a switching speed of 175 V/ns is demonstrated. Experimental results and simulations using accurate technology models confirms the theory. Keywords-Active gate driver, GaN, switching analysis, dv/dt, EMI, power electronics, ASIC for power IC.

International audience; This paper presents an AGD (active gate driver) implemented with a low voltage CMOS technology to control the dv/dt sequence of low voltage (100V) and high voltage (650V) GaN power transistors. Such an AGD can control and reduce the dv/dt of fast switching GaN devices with a reduced impact on switching losses. In the case of both low voltage and high voltage GaN fast switching transistors, such an AGD must have a total response time lower than 1ns. Therefore, introducing a feedback loop to control the dv/dt requires a specific design with a very high bandwidth (550MHz). Moreover, probing the vDS voltage and its derivative is quite challenging, as the voltage level is higher than the low voltage gate driver supply. The purpose of this work is to optimize a low voltage CMOS AGD with fully integrated functions, and implement such a solution in GaN-based power converters. Keywords-Active gate driver, GaN, switching analysis, dv/dt, EMI, power electronics, ASIC for power ic.