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1. Accelerating Time Series Analysis via Processing using Non-Volatile Memories

Author

Fernandez, Ivan, Giannoula, Christina, Manglik, Aditya, Quislant, Ricardo, Ghiasi, Nika Mansouri, Gómez-Luna, Juan, Gutierrez, Eladio, Plata, Oscar, and Mutlu, Onur

Subjects
Computer Science - Hardware Architecture
Abstract

Time Series Analysis (TSA) is a critical workload to extract valuable information from collections of sequential data, e.g., detecting anomalies in electrocardiograms. Subsequence Dynamic Time Warping (sDTW) is the state-of-the-art algorithm for high-accuracy TSA. We find that the performance and energy efficiency of sDTW on conventional CPU and GPU platforms are heavily burdened by the latency and energy overheads of data movement between the compute and the memory units. sDTW exhibits low arithmetic intensity and low data reuse on conventional platforms, stemming from poor amortization of the data movement overheads. To improve the performance and energy efficiency of the sDTW algorithm, we propose MATSA, the first Magnetoresistive RAM (MRAM)-based Accelerator for TSA. MATSA leverages Processing-Using-Memory (PUM) based on MRAM crossbars to minimize data movement overheads and exploit parallelism in sDTW. MATSA improves performance by 7.35x/6.15x/6.31x and energy efficiency by 11.29x/4.21x/2.65x over server-class CPU, GPU, and Processing-Near-Memory platforms, respectively., Comment: Published in IEEE Access, 2024, volume 12

Published
2022
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2. Exploiting Near-Data Processing to Accelerate Time Series Analysis

Author

Fernandez, Ivan, Quislant, Ricardo, Giannoula, Christina, Alser, Mohammed, Gómez-Luna, Juan, Gutiérrez, Eladio, Plata, Oscar, and Mutlu, Onur

Subjects
Computer Science - Hardware Architecture
Abstract

Time series analysis is a key technique for extracting and predicting events in domains as diverse as epidemiology, genomics, neuroscience, environmental sciences, economics, and more. Matrix profile, the state-of-the-art algorithm to perform time series analysis, computes the most similar subsequence for a given query subsequence within a sliced time series. Matrix profile has low arithmetic intensity, but it typically operates on large amounts of time series data. In current computing systems, this data needs to be moved between the off-chip memory units and the on-chip computation units for performing matrix profile. This causes a major performance bottleneck as data movement is extremely costly in terms of both execution time and energy. In this work, we present NATSA, the first Near-Data Processing accelerator for time series analysis. The key idea is to exploit modern 3D-stacked High Bandwidth Memory (HBM) to enable efficient and fast specialized matrix profile computation near memory, where time series data resides. NATSA provides three key benefits: 1) quickly computing the matrix profile for a wide range of applications by building specialized energy-efficient floating-point arithmetic processing units close to HBM, 2) improving the energy efficiency and execution time by reducing the need for data movement over slow and energy-hungry buses between the computation units and the memory units, and 3) analyzing time series data at scale by exploiting low-latency, high-bandwidth, and energy-efficient memory access provided by HBM. Our experimental evaluation shows that NATSA improves performance by up to 14.2x (9.9x on average) and reduces energy by up to 27.2x (19.4x on average), over the state-of-the-art multi-core implementation. NATSA also improves performance by 6.3x and reduces energy by 10.2x over a general-purpose NDP platform with 64 in-order cores., Comment: To appear in ISVLSI 2022 Special Session on Processing in Memory. arXiv admin note: text overlap with arXiv:2010.02079

Published
2022

6. NATSA: A Near-Data Processing Accelerator for Time Series Analysis

Author

Fernandez, Ivan, Quislant, Ricardo, Giannoula, Christina, Alser, Mohammed, Gómez-Luna, Juan, Gutiérrez, Eladio, Plata, Oscar, and Mutlu, Onur

Subjects
Computer Science - Hardware Architecture
Abstract

Time series analysis is a key technique for extracting and predicting events in domains as diverse as epidemiology, genomics, neuroscience, environmental sciences, economics, and more. Matrix profile, the state-of-the-art algorithm to perform time series analysis, computes the most similar subsequence for a given query subsequence within a sliced time series. Matrix profile has low arithmetic intensity, but it typically operates on large amounts of time series data. In current computing systems, this data needs to be moved between the off-chip memory units and the on-chip computation units for performing matrix profile. This causes a major performance bottleneck as data movement is extremely costly in terms of both execution time and energy. In this work, we present NATSA, the first Near-Data Processing accelerator for time series analysis. The key idea is to exploit modern 3D-stacked High Bandwidth Memory (HBM) to enable efficient and fast specialized matrix profile computation near memory, where time series data resides. NATSA provides three key benefits: 1) quickly computing the matrix profile for a wide range of applications by building specialized energy-efficient floating-point arithmetic processing units close to HBM, 2) improving the energy efficiency and execution time by reducing the need for data movement over slow and energy-hungry buses between the computation units and the memory units, and 3) analyzing time series data at scale by exploiting low-latency, high-bandwidth, and energy-efficient memory access provided by HBM. Our experimental evaluation shows that NATSA improves performance by up to 14.2x (9.9x on average) and reduces energy by up to 27.2x (19.4x on average), over the state-of-the-art multi-core implementation. NATSA also improves performance by 6.3x and reduces energy by 10.2x over a general-purpose NDP platform with 64 in-order cores., Comment: To appear in the 38th IEEE International Conference on Computer Design (ICCD 2020)

Published
2020

12. Hardware Support for Scratchpad Memory Transactions on GPU Architectures

Author

Villegas, Alejandro, Asenjo, Rafael, Navarro, Angeles, Plata, Oscar, Ubal, Rafael, Kaeli, David, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Rivera, Francisco F., editor, Pena, Tomás F., editor, and Cabaleiro, José C., editor

Published
2017
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14. Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems

Author

Quislant, Ricardo, Gutierrez, Eladio, Zapata, Emilio L., Plata, Oscar, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Dutot, Pierre-François, editor, and Trystram, Denis, editor

Published
2016
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17. Conflict Detection in Hardware Transactional Memory

Author

Quislant, Ricardo, Gutierrez, Eladio, Zapata, Emilio L., Plata, Oscar, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Guerraoui, Rachid, editor, and Romano, Paolo, editor

Published
2015
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20. Exploring Irregular Reduction Support in Transactional Memory

Author

Gonzalez-Mesa, Miguel A., Quislant, Ricardo, Gutierrez, Eladio, Plata, Oscar, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Kołodziej, Joanna, editor, Di Martino, Beniamino, editor, Talia, Domenico, editor, and Xiong, Kaiqi, editor

Published
2013
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21. Unified Locality-Sensitive Signatures for Transactional Memory

Author

Quislant, Ricardo, Gutierrez, Eladio D., Plata, Oscar, Zapata, Emilio L., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Jeannot, Emmanuel, editor, Namyst, Raymond, editor, and Roman, Jean, editor

Published
2011
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23. Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification

Author

Quislant, Ricardo, Gutierrez, Eladio, Plata, Oscar, Zapata, Emilio L., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Fyfe, Colin, editor, Tino, Peter, editor, Charles, Darryl, editor, Garcia-Osorio, Cesar, editor, and Yin, Hujun, editor

Published
2010
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24. Experiences with Mapping Non-linear Memory Access Patterns into GPUs

Author

Gutierrez, Eladio, Romero, Sergio, Trenas, Maria A., Plata, Oscar, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Allen, Gabrielle, editor, Nabrzyski, Jarosław, editor, Seidel, Edward, editor, van Albada, Geert Dick, editor, Dongarra, Jack, editor, and Sloot, Peter M. A., editor

Published
2009
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25. Distributed Architecture System for Computer Performance Testing

Author

Herruzo, Ezequiel, Mesones, Andrés J., Benavides, José I., Plata, Oscar, Zapata, Emilo L., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Dough, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Wyrzykowski, Roman, editor, Dongarra, Jack, editor, Meyer, Norbert, editor, and Waśniewski, Jerzy, editor

Published
2006
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29. Estudio del comportamiento de mezclas asfálticas con 100% RAP y adición de Cal hidratada.

Author

Rueda-Cárdenas, Eduardo José, dir., Duran-Plata, Oscar Darío, Gil-Vergara, Gabriel Gerardo, Rueda-Cárdenas, Eduardo José, dir., Duran-Plata, Oscar Darío, and Gil-Vergara, Gabriel Gerardo

Abstract

Este trabajo se enfoca en el uso de asfalto reciclado (RAP) y 2 porcentajes de adición de Cal del 3% y 6% más Emulsión asfáltica en frio, en las que se fabricaron probetas por cada contenido de Cal y las mismas se sometieron a diferentes tipos de ensayos los cuales a partir de los resultados nos permitieron evaluar el comportamiento físico mecánico respecto a una mezcla de control con 0% de adición de Cal.

Published
2022

30. Estudio del comportamiento de mezclas asfálticas con 100% RAP y adición de Cal hidratada.

Author

Rueda-Cárdenas, Eduardo José, Durán-Plata, Oscar Darío, Gil-Vergara, Gabriel Gerardo, Rueda-Cárdenas, Eduardo José, Durán-Plata, Oscar Darío, and Gil-Vergara, Gabriel Gerardo

Abstract

Este trabajo se enfoca en el uso de asfalto reciclado (RAP) y 2 porcentajes de adición de Cal del 3% y 6% más Emulsión asfáltica en frio, en las que se fabricaron probetas por cada contenido de Cal y las mismas se sometieron a diferentes tipos de ensayos los cuales a partir de los resultados nos permitieron evaluar el comportamiento físico mecánico respecto a una mezcla de control con 0% de adición de Cal.

Published
2022

33. Testimonios de Inmigrantes: Students Educating Future Teachers.

Author

Gonzalez, M. Saray, Plata, Oscar, Garcia, Erika, Torres, Mario, and Urrieta, Luis

Abstract

Narratives by three undocumented immigrants relate the realities of surviving in hostile and often cruel school environments. These students have succeeded not because of the system, but despite the system. Such testimonials can be effective in teaching future teachers and raising the consciousness of people who do not have sympathy for immigrants, especially immigrant children. (TD)

Published
2003

35. Estudio del comportamiento de mezclas asfálticas con 100% RAP y adición de Cal hidratada

Author

Durán-Plata, Oscar Darío, Gil-Vergara, Gabriel Gerardo, and Rueda-Cárdenas, Eduardo José

Subjects
MEZCLAS, ADICIONES, MATERIALES, CAL RAP, PAVIMENTOS
Abstract

Trabajo de Investigación Este trabajo se enfoca en el uso de asfalto reciclado (RAP) y 2 porcentajes de adición de Cal del 3% y 6% más Emulsión asfáltica en frio, en las que se fabricaron probetas por cada contenido de Cal y las mismas se sometieron a diferentes tipos de ensayos los cuales a partir de los resultados nos permitieron evaluar el comportamiento físico mecánico respecto a una mezcla de control con 0% de adición de Cal. Especialización Especialista en Ingeniería de Pavimentos INTRODUCCIÓN 1. GENERALIDADES 2. OBJETIVOS 3. MARCOS DE REFERENCIA 4. METODOLOGIA 5. CONCLUSIONES Y RECOMENDACIONES BIBLIOGRAFÍA ANEXOS

Published
2022

38. Vectorization of the radix r self-sorting FFT

Author

Amor, Margarita, Martín, María J., Blanco, Dora, Plata, Oscar G., Rivera, Francisco F., Argüello, Francisco, Goos, Gerhard, editor, Hartmanis, Juris, editor, van Leeuwen, Jan, editor, Buchberger, Bruno, editor, and Volkert, Jens, editor

Published
1994
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42. Introduction

Author

Chapman, Barbara, Kienhuis, Bart, Ayguadé, Eduard, Bodin, François, Plata, Oscar, Stotzer, Eric, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Sips, Henk, editor, Epema, Dick, editor, and Lin, Hai-Xiang, editor

Published
2009
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43. Teaching the cache memory system using a reconfigurable approach

Author

Quislant, Ricardo, Herruzo, Ezequiel, Plata, Oscar, Benavides, Jose Ignacio, and Zapata, Emilio L.

Subjects
Cache memory -- Study and teaching, Disk caching -- Study and teaching, Computer-generated environments -- Educational aspects, Computer simulation -- Educational aspects, Computer architecture -- Study and teaching, Cache memory, Business, Education, Electronics, Electronics and electrical industries
Abstract

This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the instruction set architecture (ISA) level. The proposed tool simulates a cache system that can be reconfigured within a variety of 298 combinations of cache capacity, number of ways or associativity, and line/block size in words (C, W, and L) without changing its architecture. The simulator was developed through a series of laboratory exercises in computer architecture. The students are introduced to the reconfigurable cache architecture while refreshing their knowledge on computer architecture issues like logic design, and register transfer level and computer system level architectures, as well as reinforcing concepts about memory system organization and architecture. This paper presents an overview of the reconfigurable cache and a description of the simulator interface. Finally, feedback from the students provides assessment on using the simulator in the laboratory. Index Terms--Cache memories, computer-aided instruction, education, reconfigurable cache design, simulation software.

Published
2008

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