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Carbon nanotube (CNT) transistors demonstrate high mobility but also experience off-state leakage due to the small effective mass and band gap. The lower limit of off-current ( I MIN ) was measured in electrostatically doped CNT metal-oxide-semiconductor field-effect transistors (MOSFETs) across a range of band gaps (0.37 to 1.19 eV), supply voltages (0.5 to 0.7 V), and extension doping levels (0.2 to 0.8 carriers/nm). A nonequilibrium Green's function (NEGF) model confirms the dependence of I MIN on CNT band gap, supply voltage, and extension doping level. A leakage current design space across CNT band gap, supply voltage, and extension doping is projected based on the validated NEGF model for long-channel CNT MOSFETs to identify the appropriate device design choices. The optimal extension doping and CNT band gap design choice for a target off-current density are identified by including on-current projection in the leakage current design space. An extension doping level >0.5 carrier/nm is required for optimized on-current.

A new generation of compact and high-speed electronic devices, based on carbon, would be enabled through the development of robust gate oxides with sub-nanometer effective oxide thickness (EOT) on carbon nanotubes or graphene nanoribbons. However, to date, the lack of dangling bonds on sp 2 oriented graphene sheets has limited the high precursor nucleation density enabling atomic layer deposition of sub-1 nm EOT gate oxides. It is shown here that by deploying a low-temperature AlO x (LT AlO x ) process, involving atomic layer deposition (ALD) of Al 2 O 3 at 50 °C with a chemical vapor deposition (CVD) component, a high nucleation density layer can be formed, which templates the growth of a high- k dielectric, such as HfO 2 . Atomic force microscopy (AFM) imaging shows that at 50 °C, the Al 2 O 3 spontaneously forms a pinhole-free, sub-2 nm layer on graphene. Density functional theory (DFT) based simulations indicate that the spreading out of AlO x clusters on the carbon surface enables conformal oxide deposition. Device applications of the LT AlO x deposition scheme were investigated through electrical measurements on metal oxide semiconductor capacitors (MOSCAPs) with Al 2 O 3 /HfO 2 bilayer gate oxides using both standard Ti/Pt metal gates as well as TiN/Ti/Pd gettering gates. In this study, LT AlO x was used to nucleate HfO 2 and it was shown that bilayer gate oxide stacks of 2.85 and 3.15 nm were able to achieve continuous coverage on carbon nanotubes (CNTs). The robustness of the bilayer was tested through deployment in a CNT-based field-effect transistor (FET) configuration with a gate leakage of less than 10 -8 A/μm per CNT.

Advanced beyond-silicon electronic technology requires both channel materials and also ultralow-resistance contacts to be discovered 1,2 . Atomically thin two-dimensional semiconductors have great potential for realizing high-performance electronic devices 1,3 . However, owing to metal-induced gap states (MIGS) 4-7 , energy barriers at the metal-semiconductor interface-which fundamentally lead to high contact resistance and poor current-delivery capability-have constrained the improvement of two-dimensional semiconductor transistors so far 2,8,9 . Here we report ohmic contact between semimetallic bismuth and semiconducting monolayer transition metal dichalcogenides (TMDs) where the MIGS are sufficiently suppressed and degenerate states in the TMD are spontaneously formed in contact with bismuth. Through this approach, we achieve zero Schottky barrier height, a contact resistance of 123 ohm micrometres and an on-state current density of 1,135 microamps per micrometre on monolayer MoS 2 ; these two values are, to the best of our knowledge, the lowest and highest yet recorded, respectively. We also demonstrate that excellent ohmic contacts can be formed on various monolayer semiconductors, including MoS 2 , WS 2 and WSe 2 . Our reported contact resistances are a substantial improvement for two-dimensional semiconductors, and approach the quantum limit. This technology unveils the potential of high-performance monolayer transistors that are on par with state-of-the-art three-dimensional semiconductors, enabling further device downscaling and extending Moore's law.

Vanadium dioxide (VO 2 ) has been widely studied for its rich physics and potential applications, undergoing a prominent insulator-metal transition (IMT) near room temperature. The transition mechanism remains highly debated, and little is known about the IMT at nanoscale dimensions. To shed light on this problem, here we use ∼1 nm-wide carbon nanotube (CNT) heaters to trigger the IMT in VO 2 . Single metallic CNTs switch the adjacent VO 2 at less than half the voltage and power required by control devices without a CNT, with switching power as low as ∼85 μW at 300 nm device lengths. We also obtain potential and temperature maps of devices during operation using Kelvin probe microscopy and scanning thermal microscopy. Comparing these with three-dimensional electrothermal simulations, we find that the local heating of the VO 2 by the CNT plays a key role in the IMT. These results demonstrate the ability to trigger IMT in VO 2 using nanoscale heaters and highlight the significance of thermal engineering to improve device behavior.

As the physical dimensions of a transistor gate continue to shrink to a few atoms, performance can be increasingly determined by the limited electronic density of states (DOS) in the gate and the gate quantum capacitance ( C Q ). We demonstrate the impact of gate C Q and the dimensionality of the gate electrode on the performance of nanoscale transistors through analytical electrostatics modeling. For low-dimensional gates, the gate charge can limit the channel charge, and the transfer characteristics of the device become dependent on the gate DOS. We experimentally observe for the first time, room-temperature gate quantization features in the transfer characteristics of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) channel transistors; features which can be attributed to the Van Hove singularities in the one-dimensional DOS of the CNT gate. In addition to being an important aspect of future transistor design, potential applications of this phenomenon include multilevel transistors with suitable transfer characteristics obtained via engineered gate DOS.

The recent surge of interest in brain-inspired computing and power-efficient electronics has dramatically bolstered development of computation and communication using neuron-like spiking signals. Devices that can produce rapid and energy-efficient spiking could significantly advance these applications. Here we demonstrate direct current or voltage-driven periodic spiking with sub-20 ns pulse widths from a single device composed of a thin VO 2 film with a metallic carbon nanotube as a nanoscale heater, without using an external capacitor. Compared with VO 2 -only devices, adding the nanotube heater dramatically decreases the transient duration and pulse energy, and increases the spiking frequency, by up to 3 orders of magnitude. This is caused by heating and cooling of the VO 2 across its insulator-metal transition being localized to a nanoscale conduction channel in an otherwise bulk medium. This result provides an important component of energy-efficient neuromorphic computing systems and a lithography-free technique for energy-scaling of electronic devices that operate via bulk mechanisms.

Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for flexible and wearable electronics. However, it usually suffers from low semiconducting tube purity, low device yield, and the mismatch between p- and n-type TFTs. Here, we report low-voltage and high-performance digital and analog CNT TFT circuits based on high-yield (19.9%) and ultrahigh purity (99.997%) polymer-sorted semiconducting CNTs. Using high-uniformity deposition and pseudo-CMOS design, we demonstrated CNT TFTs with good uniformity and high performance at low operation voltage of 3 V. We tested forty-four 2-µm channel 5-stage ring oscillators on the same flexible substrate (1,056 TFTs). All worked as expected with gate delays of 42.7 ± 13.1 ns. With these high-performance TFTs, we demonstrated 8-stage shift registers running at 50 kHz and the first tunable-gain amplifier with 1,000 gain at 20 kHz. These results show great potentials of using solution-processed CNT TFTs for large-scale flexible electronics.

Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of very large scale integration circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Low-temperature fabrication (e.g., <400 °C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance, in series with the channel resistance, reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work, we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact lengths. These CNFET contacts are ∼15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length, allowing for multiple generations of future scaling of the transistor-contacted gate pitch. For the 10 nm contacts, we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at V DS = 0.7 V compared with the best reported 200 nm contacts to date, corroborated by results in this work. Our analysis of R C from 232 single-CNT CNFETs between the long-contact (e.g., 200 nm) and short-contact (e.g., 10 nm) regimes quantifies the resistance variation and projects the impact on CNFET current variability versus the number of CNT in the transistor. The resistance distribution reveals contact-length-dependent R C variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact-length-independent resistance variation, we analyze the variation of R C in arrays of identical CNFETs along a single CNT of constant diameter and observe the random occurrence of high  R C , even on correlated CNFETs.

Selective extraction of semiconducting carbon nanotubes is a key step in the production of high-performance, solution-processed electronics. Here, we describe the ability of a supramolecular sorting polymer to selectively disperse semiconducting carbon nanotubes from five commercial sources with diameters ranging from 0.7 to 2.2 nm. The sorting purity of the largest-diameter nanotubes (1.4 to 2.2 nm; from Tuball) was confirmed by short channel measurements to be 97.5%. Removing the sorting polymer by acid-induced disassembly increased the transistor mobility by 94 and 24% for medium-diameter and large-diameter carbon nanotubes, respectively. Among the tested single-walled nanotube sources, the highest transistor performance of 61 cm 2 /V·s and on/off ratio >10 4 were realized with arc discharge carbon nanotubes with a diameter range from 1.2 to 1.7 nm. The length and quality of nanotubes sorted from different sources is compared using measurements from atomic force microscopy and Raman spectroscopy. The transistor mobility is found to correlate with the G/D ratio extracted from the Raman spectra.

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS 2 ) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~10 6 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state., (Copyright © 2016, American Association for the Advancement of Science.)

High-purity semiconducting single-walled carbon nanotubes (s-SWNTs) with little contamination are desired for high-performance electronic devices. Although conjugated polymer wrapping has been demonstrated as a powerful and scalable strategy for enriching s-SWNTs, this approach suffers from significant contaminations by polymer residues and high cost of conjugated polymers. Here, we present a simple but general approach using removable and recoverable conjugated polymers for separating s-SWNTs with little polymer contamination. A conjugated polymer with imine linkages was synthesized to demonstrate this concept. Moreover, the SWNTs used are without prepurifications and very low cost. The polymer exhibits strong dispersion for large-diameter s-SWNTs with high yield (23.7%) and high selectivity (99.7%). After s-SWNT separation, the polymer can be depolymerized into monomers and be cleanly removed under mild acidic conditions, yielding polymer-free s-SWNTs. The monomers can be almost quantitatively recovered to resynthesize polymer. This approach enables isolation of "clean" s-SWNTs and, at the same time, greatly lowers costs for SWNT separation.

The electronic properties of solution-processable small-molecule organic semiconductors (OSCs) have rapidly improved in recent years, rendering them highly promising for various low-cost large-area electronic applications. However, practical applications of organic electronics require patterned and precisely registered OSC films within the transistor channel region with uniform electrical properties over a large area, a task that remains a significant challenge. Here, we present a technique termed "controlled OSC nucleation and extension for circuits" (CONNECT), which uses differential surface energy and solution shearing to simultaneously generate patterned and precisely registered OSC thin films within the channel region and with aligned crystalline domains, resulting in low device-to-device variability. We have fabricated transistor density as high as 840 dpi, with a yield of 99%. We have successfully built various logic gates and a 2-bit half-adder circuit, demonstrating the practical applicability of our technique for large-scale circuit fabrication.

Dense alignment of single-walled carbon nanotubes over a large area is demonstrated using a novel solution-shearing technique. A density of 150-200 single-walled carbon nanotubes per micro-meter is achieved with a current density of 10.08 μA μm(-1) at VDS = -1 V. The on-current density is improved by a factor of 45 over that of random-network single-walled carbon nanotubes., (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.)

A highly sensitive single-walled carbon nanotube/C60 -based infrared photo-transistor is fabricated with a responsivity of 97.5 A W(-1) and detectivity of 1.17 × 10(9) Jones at 1 kHz under a source/drain bias of -0.5 V. The much improved performance is enabled by this unique device architecture that enables a high photoconductive gain of ≈10(4) with a response time of several milliseconds., (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.)

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (∼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.