1. Impact of the recessed gate depth on the GaN metal-oxide-semiconductor high electron mobility transistor performances: New insights on mobility extraction.
- Author
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Piotrowicz, C., Mohamad, B., Malbert, N., Bécu, S., Ruel, S., and Le Royer, C.
- Subjects
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METAL oxide semiconductor capacitors , *MODULATION-doped field-effect transistors , *METAL oxide semiconductor field-effect transistors , *GALLIUM nitride , *ELECTRON mobility , *COMPUTER-aided design , *PLASMA etching , *STRAY currents - Abstract
This paper provides a comprehensive study of the impact of the gate recess depth (RD) on the GaN-on-Si MOS-HEMTs DC performances. IDS = f(VGS) and IDS = f(VDS) measurements are conducted at 25 and 150 °C, respectively, in forward and blocking modes. The gate recessed depth (50, 150, and 350 nm) is modulated by adjusting the plasma etching time, which is a critical step for improving the dielectric/GaN interface quality and the gate channel electron mobility. Three distinct regions can be defined separately: the bottom, the sidewall, and the corner region being the junction between the two previous regions. To assess the impact of gate recessed depth (RD) on the several mobilities around the gate cavity first, we applied our previous methodology allowing us to extract the bottom (μbot) and the entire sidewall region mobility (μT), without distinction from the corner. The mobility of the transverse region was found surprisingly to increase with deeper RD. To gain insight into the impact of the RD on this transverse section, a new extraction methodology is proposed to extract separately the gate corner (μcorner) and sidewall (μSW) mobility. These extractions show that the corner mobility is found to be reduced compared to the sidewall one (μcorner < μSW) evidencing the different weighting contributions over the transverse mobility. Moreover, these mobilities are found to be more degraded compared to the bottom one, highlighting the different contributions on the on-state resistance (RON). Indeed, the on-state resistance is lowered with the shallower RD due to the reduced sidewall resistance contribution (lower sidewall length) and despite the incremental contribution of the bottom resistance (larger effective gate length). However, the shallower RD shows an increase in the drain–source leakage current in reason of a lower gate electrostatic control. Technology Computer Aided Design (TCAD) simulations of the three RD morphologies are carried out to validate the experimental trends and the proposed methodology. [ABSTRACT FROM AUTHOR]
- Published
- 2024
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