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Flying capacitor multilevel (FCML) converters typically rely on natural balancing to achieve a balanced distribution of flying capacitor voltages. The mechanisms by which the flying capacitor voltages are able to balance have been extensively studied and theoretically there are certain combinations of level count and duty cycle at which the flying capacitor voltages do not balance. Although the flying capacitor voltages should diverge from the balanced distribution, in practice this behavior is rarely observed. To resolve this discrepancy between FCML converter theory and experiment, this article analyzes the impact of switch output capacitance on the flying capacitor voltage balancing dynamics, and illustrates that this capacitance has a naturally balancing effect. The additional mechanism of switch output capacitance induced balancing is analytically described and compared against experimental results on several FCML converter prototypes.

This work presents a capacitor voltage balancing controller for current-controlled flying capacitor multilevel converters. A small-signal model of the converter derived from state–space averaging informs the parallel controller structure. The proposed controller incorporates nonlinear actions to decouple flying capacitor control loops and prevent adverse interaction between the capacitor voltage balancing and inductor current controllers. Experimental results of closed-loop line and load transient responses demonstrate significant performance improvements with the proposed balancing architecture compared to a converter relying on natural capacitor balancing. These improvements are quantified with experimental measurements of switch voltage stress and load current disturbance as a response to line voltage perturbations at different frequencies. Limits to control bandwidths in balancing controllers based on averaged models are discussed. The closed-loop stability of the converter operating with the proposed active balancing architecture is discussed as a function of the operating point, controller gains, and hardware parameters, such as output filter inductance and inductor current ripple.

This article proposes an ultra-high-current 48-V-to-1-V hybrid switched-capacitor (SC) voltage regulator, named the switching bus converter, with a single-stage vertical power delivery architecture for next-generation ultra-high-power processors (e.g., graphics processing units, central processing units, application-specific integrated circuits, etc.). The proposed topology consists of two 2-to-1 SC front-ends and four 10-branch series-capacitor-buck modules, merged through four switching buses. Compared to the existing dc-bus-based architecture, the proposed switching-bus-based architecture eliminates the need for dc bus capacitors, reduces the switch count, and guarantees complete soft-charging operation. Through a topological comparison, this article reveals that the proposed topology achieves the lowest normalized switch stress and the smallest normalized passive component volume among existing 48-V-to-1-V hybrid SC demonstrations, showing great potential for both higher efficiency and higher power density than prior hybrid SC solutions. A hardware prototype was designed and built with custom four-phase coupled inductors and gate drive daughterboards to validate the functionality and performance of the proposed switching bus converter. It was tested up to 1500-A output current and achieved 92.7% peak system efficiency, 85.7% full-load system efficiency (including gate drive loss), and 759 W/in$^{3}$ power density (by box volume), pushing the performance limit of the state-of-the-art 48-V-to-1-V solutions toward higher efficiency and higher power density.

The conventional dc-link aluminum electrolytic capacitor bank simply, efficiently, and cost-effectively decouples the instantaneous power mismatch inherent to all single-phase ac–dc power converters. However, the practical realization of the capacitor bank remains largely qualitative and dependent on the opaque performance capabilities of the capacitor technology. This work presents an exhaustive survey of commercial aluminum electrolytic capacitors and defines both quantitative and justly comparative device-level figures-of-merit (FOM). By configuring the relative voltage ripple ratio specification $\alpha$ of the dc bus, these device FOM enable the determination of minimal dc-link capacitor volume, cost, and/or mass. Graphical illustration demonstrates that the set of commercially available yet viable components diminishes as specification $\alpha$ increases; the realized dc-link capacitor bank volume and cost will grow appreciably for ${\alpha >\!10\,{\%}}$ and ${\alpha >\!5\,{\%}}$, respectively.

This article presents a general analytical framework enabling the large-signal characterization of resonant switched-capacitor (ReSC) power converters that accounts for passive component voltage and current ripple, for operation at and above resonance. From this, appropriate phase durations for minimized rms currents are derived, in addition to expressions for total passive component volume using an intuitive peak energy method. An example hardware prototype validates both the derived waveforms and timings—as well as total passive volume—through three comparable hardware configurations, one of which minimizes passive component volume. In addition, the proposed technique formulates analytical expressions for both rms currents and peak blocking voltages, facilitating refined loss estimation and component selection. Subsequent calculation of the large-signal volt-amp switch stress metric allows a more accurately quantified tradeoff between active and passive components compared to prior work, which has not fully accounted for ripple. Four common ReSC topologies are exemplified throughout, with topology-specific parameters documented for reference.

In pre-existing analytical models of switched-capacitor (SC) converters, the input and output capacitances ($C_{\text{in}}$ and $C_{\text{out}}$) have long been assumed to be infinitely large so that the input and output can be modeled as ideal voltage sources. However, in practice, the terminal capacitances can be insufficient to ensure ideal input and output behaviors due to space and cost constraints. This article reveals that finite terminal capacitances can have considerable effects on the output impedance ($R_{\text{out}}$) and overall efficiency of SC converters. A general modeling and analysis methodology is proposed for SC converters to characterize the effects of finite terminal capacitances quantitatively. A 2-to-1 SC converter prototype is specially designed to verify the proposed general output impedance model. The relative error between the modeling results and the experimental measurements is less than 8%, which demonstrates the excellent accuracy of the proposed model. It is revealed that the insufficiency in $C_{\text{in}}$ can lead to a considerably higher $R_{\text{out}}$ and harm the overall efficiency. On the contrary, decreasing $C_{\text{out}}$ can counter-intuitively help reduce $R_{\text{out}}$, which contributes to both higher efficiency and higher power density, although this benefit comes at the cost of a larger output voltage ripple. In addition, $C_{\text{out}}$ has a stronger effect on $R_{\text{out}}$ in the slow switching region, while $C_{\text{in}}$ is more influential in the fast switching region, especially around the knee of the output impedance curve, which is the typical operating point of SC converters. Several design guidelines are provided based on these findings. Further discussions are provided to explain how to apply the proposed general output impedance model to arbitrary SC topologies.

This work introduces the symmetric dual inductor hybrid (SDIH) dc–dc converter topology, which is suitable for large conversion ratios where regulation is required, such as direct 48 V to point-of-load (PoL) applications. A Dickson-type switched capacitor network is used to effectively produce two interleaved pulsewidth-modulated (PWM) outputs with a greatly reduced voltage amplitude relative to the input voltage, allowing the subsequent magnetic volume to be reduced while retaining modest switching frequencies. Distinct from related variations, part count is significantly reduced while both even and odd order switched capacitor networks can be used with straightforward split-phase control; allowing either network type to achieve complete soft-charging of all flying capacitors. Additionally, charge flow is uniformly distributed through all elements, with equal capacitor and inductor values being preferred. Subsequently, this topology is expected to simplify component selection, improve electrical and thermal performance, and reduce cost. Furthermore, analysis is presented that calculates precise phase durations without making small ripple assumptions, revealing up to a 75% timing error in cases where either inductor or capacitor ripple is ignored. Finally, a discrete prototype validates this analysis and demonstrates very high measured power densities of 1029, 754, and 663 W/in$^{3}$ for 48 V input and regulated output voltages of 3, 2, and 1 V, respectively, while switching at a frequency of 750 kHz.