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In this paper, two improved ultra-wideband (UWB) balanced power amplifiers based on the flip-chip system-in-package technique and electronic design automation (EDA) are proposed. The conventional approach to system-on-chip (SoC) involves integrating all sub-circuit designs into a single manufacturing process. However, in radio frequency circuits, adopting the SoC approach necessitates intricate matching designs, leading to an increase in development costs. In this study, two types of SiGe unit power amplifiers attempted to achieve a flat S21 response using simpler matching for input/output. The cascode architecture was adopted as the main structure for the first type of unit power amplifier (type I). Subsequently, the design of the second type unit power amplifier was built upon the foundation of the first type, with the only difference being the implementation of two parallel cascode structures (type II), and the primary goal is to enhance both gain and output power compared to the first type. In addition, for this second type unit power amplifier, in conjunction with a quadrature hybrid coupler, the optimal impedance matching value was selected to maintain the flatness of gain across the entire UWB range. Furthermore, the poor performance of S11,22 of these two types of unit power amplifiers was improved by using quadrature hybrid couplers using the WIPD process combined with EDA simulation. Therefore, using flip-chip packaging technology can effectively reduce the increased wafer fabrication costs caused by complex matching designs in active circuits. This improved system has the potential to offer a new practical application for UWB power amplifier design.

This paper designs two single-stage LC-tank injection-locked frequency sixtuplers (ILFSs) fabricated in a 90 nm CMOS process and it describes the circuit design, operation principle, and measurement results of the ILFSs. The ILFS circuit with a differential input and single-phase output is made of a first-harmonic injection-locked oscillator (ILO), a frequency tripler, and a push-push doubler. The first ILFS uses an octagonal inductor. For a supply voltage of 0.4 V, the free-running frequency is around 41.52 GHz, DC power consumption is 9.03 mW at the incident power of 0 dBm, and the output locking range at 0 dBm input power is 10.21 %. The second ILFS uses an 8-shaped inductor for low electromagnetic (EM) noise generation. The free-running frequency is around 37.2 GHz, DC power consumption is 7.72 mW at the incident power of 0 dBm, and the output locking range at 0 dBm input power is 17.4 %. The two chips have the same area, $0.7\times0.7$ mm2. This paper also provides a further analysis and comparison of the RF performance of on-chip inductors designed. Simulation shows the substrate noise coupling and distance noise coupling between victim and aggressor, the 8-shaped inductor exhibits a significant reduction in coupling. By the measurement results, it is evident that the performance of the 8-shaped inductor ILFS is superior to that of the octagonal inductor ILFS.