98 results on '"Philippe Marquet"'
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2. SCAC: Weakly-coupled execution model for massively parallel systems.
3. SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC.
4. Master-Slave Control Structure for Massively Parallel System on Chip.
5. Broadcast with mask on a massively parallel processing on a chip.
6. A model-driven based framework for rapid parallel SoC FPGA prototyping.
7. Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip.
8. IP Based Configurable SIMD Massively Parallel SoC.
9. FPGA-based many-core System-on-Chip design.
10. Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA.
11. Repetitive Allocation Modelling with MARTE.
12. Model Transformations for the Compilation of Multi-processor Systems-on-Chip.
13. Multiple Abstraction Views of FPGA to Map Parallel Applications.
14. A Design Flow to Map Parallel Applications onto FPGAs.
15. Multilevel MPSOC simulation using an MDE approach.
16. Massively parallel processing on a chip.
17. FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar.
18. Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies.
19. SOAP Based Distributed Simulation Environment for SoC Design.
20. Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP.
21. Ther Drug Monit
22. UML2 as an ADL Hierarchichal Hardware Modeling.
23. Design of a Real-Time Scheduler for Kahn Process Networks on Multiprocessor Systems.
24. MDA for SoC Design, Intensive Signal Processing Experiment.
25. GASPARD - A Visual Parallel Programming Environment.
26. Visual Data-Parallel Programming for Signal Processing Applications.
27. Compilation Principle of a Specification Language Dedicated to Signal Processing.
28. A fast MPSoC virtual prototyping for intensive signal processing applications.
29. A Model-Driven Design Framework for Massively Parallel Embedded Systems.
30. Scalable mpNoC for massively parallel systems - Design and implementation on FPGA.
31. Irregular Data-Parallel Objects in C++.
32. Supporting Irregular and Dynamic Computations in Data Parallel Languages.
33. Mixed synchronous-asynchronous approach for real-time image processing: a MPEG-like coder.
34. Analysis of Synchronous Dynamic Load Balancing Algorithms.
35. Dynamic Load Balancing on SIMD Data-Parallel Computers.
36. A Data-Parallel View of the Load Balancing - Experimental Results on MasPar MP-1.
37. HELP for parallel scientific programming.
38. HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages.
39. DPFS: A Data-Parallel File System Environment.
40. Real-time systems for multiprocessor architectures.
41. Data-Parallel Load Balancing Strategies.
42. An Asymmetric Real-Time Scheduling for Linux.
43. A Geometrical Data-Parallel Language.
44. Référentiel de connaissances pour un numérique éco-responsable
45. EVA: an explicit vector language.
46. Vector addressing processor for direct and indirect accesses.
47. DIU �� Enseigner l���informatique au lyc��e��
48. Une analyse des exercices d’algorithmique et de programmation du brevet 2017
49. Performance improvement for vector pipeline multiprocessor systems using a disordered execution model.
50. L codent, L créent: créations numériques artistiques pour démystifier l'informatique... au féminin! (descriptif d’atelier)
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