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Optoelectronic systems can exert precise control over targeted neurons and pathways throughout the brain in untethered animals, but similar technologies for the spinal cord are not well established. In the present study, we describe a system for ultrafast, wireless, closed-loop manipulation of targeted neurons and pathways across the entire dorsoventral spinal cord in untethered mice. We developed a soft stretchable carrier, integrating microscale light-emitting diodes (micro-LEDs), that conforms to the dura mater of the spinal cord. A coating of silicone-phosphor matrix over the micro-LEDs provides mechanical protection and light conversion for compatibility with a large library of opsins. A lightweight, head-mounted, wireless platform powers the micro-LEDs and performs low-latency, on-chip processing of sensed physiological signals to control photostimulation in a closed loop. We use the device to reveal the role of various neuronal subtypes, sensory pathways and supraspinal projections in the control of locomotion in healthy and spinal-cord injured mice., Optogenetics is applied to the entire mouse spinal cord.

This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), which relies on gate delay in the time domain, power-efficient quantization of PE by the proposed conversion scheme in the FDV domain can be accomplished with a higher power-supply/common-mode rejection ratio (PSRR/CMRR), lower process, voltage, and temperature (PVT) sensitivity, finer resolution, and better linearity. The implemented DPLL covers the fractional-N operation by a 10-bit differential current digital-to-analog converter (DAC) with a resistive load to represent the fractional phase/time. A differential $dv/dt$ ramp is employed to linearly transfer the preset initial voltage into a small phase/voltage error, which is digitized by a narrow-range fine-resolution 7-bit self-timed successive-approximation-register analog-to-digital converter (SAR-ADC). The prototype DPLL, implemented in 130-nm CMOS, achieves 101-fs rms jitter, integrated from 10 kHz to 40 MHz, in the fractional-N mode with sub-12-bit fractional-frequency-control words, using an 80-MHz reference clock (REF), consuming 9.2 mW. This corresponds to a figure of merit (FoM) of −250.3 dB. The measured worst case fractional spur level is −56 dBc.

Activation of nociceptor sensory neurons by noxious stimuli both triggers pain and increases capillary permeability and blood flow to produce neurogenic inflammation1,2, but whether nociceptors also interact with the immune system remains poorly understood. Here we report a neurotechnology for selective epineural optogenetic neuromodulation of nociceptors and demonstrate that nociceptor activation drives both protective pain behavior and inflammation. The wireless optoelectronic system consists of sub-millimeter-scale light-emitting diodes embedded in a soft, circumneural sciatic nerve implant, powered and driven by a miniaturized head-mounted control unit. Photostimulation of axons in freely moving mice that express channelrhodopsin only in nociceptors resulted in behaviors characteristic of pain, reflecting orthodromic input to the spinal cord. It also led to immune reactions in the skin in the absence of inflammation and potentiation of established inflammation, a consequence of the antidromic activation of nociceptor peripheral terminals. These results reveal a link between nociceptors and immune cells, which might have implications for the treatment of inflammation.

This paper presents a Fractional-N (Frac-N) digital phase-locked loop (DPLL) that resolves phase error (PE) in fully differential voltage (FDV) domain, where power-efficient PE detection can be accomplished with higher CMRR, lower PVT sensitivity, finer resolution and better linearity as compared to gate delay-dependent time domain. The implemented DPLL covers the frac-N operation by a 10b DAC in voltage domain (V-domain). A differential dv/dt ramp is employed to linearly transfer the frac-N phase difference into a small range voltage error, which is digitized by a narrow range but fine resolution 7b ADC. The DPLL achieves an integrated RMS jitter of 101fs with −56dBc worst-case fractional spur and consumes 9.2mW which translates to a FoM of −250.3dB.

We report VivoSoC , a system-on-chip realized in 130-nm CMOS for miniaturized medical instrumentation as used in mobile health devices or implantable telemetry systems for animal experiments. It features six neural stimulation channels and acquisition circuits for 9 $\times $ electrode-based recordings, 4-channel/32-LED photoplethysmography (PPG), bioimpedance, and temperature. A 34- $\mu \text{W}$ /MHz quad-core processing unit with sophisticated data, power, and clock management techniques enables on-chip feature extraction, which can dramatically reduce transmission or storage data rates in a system—crucial for overall power consumption and exemplarily demonstrated on preliminary work on implantable PPG-based vital signs monitoring.

We report preliminary work on an implantable telemetry device for photo-plethysmography based vital signs monitoring with a recently reported multi-sensor and parallel processing system-on-chip. The envisioned system would enable monitoring of arterial oxygenation, heart rate, blood pressure and respiration rate with a single optical probe implanted on an artery — a less invasive method than the current state-of-the-art.

We report a system-on-chip (SoC) realised in 130nm CMOS for implantable telemetry systems and mobile health applications featuring 6 neural stimulation channels and acquisition circuits for 9× electrode-based recordings (ExG), 4×/32× photo-plethysmography (PPG), bio-impedance, and temperature. The SoC includes a low-power quad-core processor (34μW/MHz) with sophisticated power and clock management - enabling power-gating, load-aware voltage scaling, and selective clock-gating. The latter is demonstrated on the example of preliminary work on an implantable telemetry device for vital signs monitoring.

We report a photo-plethysmography ASIC realised in a 130nm CMOS technology, which supports multi-channel probe configurations with up to 32 LEDs and 4 photodiodes. The receiver can cover a wide range of (full-scale) input signal strengths between 13nA and 63μA. In a typical pulse oximetry application (0.1–20Hz), overall loop dynamic range is 96dB, with noise contributions by the driver, LED, photodiode and receiver all taken into account. Total power consumption is 5.9mW, including two LEDs pulsed at 600Hz and 50mA. Compared to the state-of-the-art a saving of 68% has been achieved for equal signal quality.

We present ongoing work on a platform for mobile health and implantable telemetry devices with powerful point-of-contact processing capabilities based on our VivoSoC multi-sensor medical instrumentation SoC, a custom power management IC, and only a few additional components - allowing the realisation of sub-ccm devices. We detail the powerful yet efficient acquisition and parallel processing capabilities on the example of first applications, demonstrate system- and chip-level power management and address the application-layer considerations of a file system optimised for serial flash devices and job scheduling.

Considerable progress has been made in the last decade in implantable bioelectronic neurosystems. Yet most neural implants are used in acute and tethered experimental conditions. Here, we present a preliminary prototype of a multichannel system for simultaneous peripheral nerve stimulation and neural recording. The system comprises miniaturized electronics with a total volume of less then 1.4cm 3 including a 3.7V battery which is expected to last for 94 days of standby operation or 18 hours of continuous recording and stimulation. Data read-out and device configuration are wireless. Visceral nerves in rodents are interfaced with compliant extraneural electrodes. The 100×350μm 2 electrodes display a low impedance (1.8kn at 1kHz) with a PEDOT:PSS coating. We validated the prototype in acute experiments by applying electrical stimulation to the aortic depressor nerve (ADN), resulting in effective and reproducible decrease in blood pressure and heart rate. The combination of miniaturized electronics and flexible electrodes makes the presented system a versatile platform for future implantable devices interfacing small peripheral nerves and potentially enables new applications in the field of neuroscience.

Wearable devices offer interesting features, such as low cost and user friendliness, but their use for medical applications is an open research topic, given the limited hardware resources they provide. In this paper, we present an embedded solution for real-time EMG-based hand gesture recognition. The work focuses on the multi-level design of the system, integrating the hardware and software components to develop a wearable device capable of acquiring and processing EMG signals for real-time gesture recognition. The system combines the accuracy of a custom analog front end with the flexibility of a low power and high performance microcontroller for on-board processing. Our system achieves the same accuracy of high-end and more expensive active EMG sensors used in applications with strict requirements on signal quality. At the same time, due to its flexible configuration, it can be compared to the few wearable platforms designed for EMG gesture recognition available on market. We demonstrate that we reach similar or better performance while embedding the gesture recognition on board, with the benefit of cost reduction. To validate this approach, we collected a dataset of 7 gestures from 4 users, which were used to evaluate the impact of the number of EMG channels, the number of recognized gestures and the data rate on the recognition accuracy and on the computational demand of the classifier. As a result, we implemented a SVM recognition algorithm capable of real-time performance on the proposed wearable platform, achieving a classification rate of 90%, which is aligned with the state-of-the-art off-line results and a 29.7 mW power consumption, guaranteeing 44 hours of continuous operation with a 400 mAh battery.

The observation of eye movements has become a widely accepted technique in several research areas and the demand for mobile, out-of-lab eye trackers has steadily increased. Most of these head-mounted systems use videooculography (VOG) to record eye movements. VOG systems operate on low sampling rates around 30 to 60 Hz. Sampling rates this low, can hamper the undistorted analysis of the dynamic properties of eye movements. This paper presents an electrooculography (EOG) based, head-mounted eye tracker with a sampling rate of 1kHz — a temporal resolution high enough for acquisition of all eye movements and their dynamic properties (e.g. peak velocity). A compact data acquisition device stores the data and provides a real-time preview on a mobile device. The system achieves a EOG-inherent spatial resolution of 1.6 °. A wide-angle scene camera enables the recording of the participant's field of view. The system is intended as out-of-lab eye tracker, for example in the context of an objective fitness-to-drive test for the elderly, and poses a high sampling alternative to VOG-based eye trackers.

In battery-powered medical instrumentation, the resolution and signal bandwidth of analog-to-digital converters (ADCs) have to be adapted to the needs of the application to avoid power wastage. This paper presents a reconfigurable successive approximation register (SAR) ADC implemented in 130 nm CMOS that resolves 5–14 bit with a maximum achievable effective number of bits (ENOB) of 13.5 using non-subtractive dither. In the proposed ADC design, the power consumption can be traded for accuracy to improve the energy efficiency and extend its application range, while reducing system integration complexity. A figure-of-merit (FoM) of 59 fJ/conversion is achieved at 1.2 V supply and the converter occupies an area of 0.42 ${\rm mm}^{2}$ . Measurement results of the ADC integrated in a multi-channel analog front-end (AFE) circuit show the suitability of the ADC for portable medical monitoring devices.

Conditioning and processing of biological signals represent interesting challenges for wearable electronics in health applications. Information gathering from these signals requires complex hardware circuitry and dedicated computation resources. The design of innovative analog front-end integrated circuits, combined with efficient signal processing algorithms, allows the development of platforms for monitoring, activity and gesture recognition based on embedded real-time systems. This paper describes an Electromyography pattern recognition system based on the combination of low cost passive sensors, an innovative analog front-end and a low power microcontroller. The performance of the proposed system matches state-of-the-art high-end active sensors, opening the way to the development of affordable and accurate wearable devices.

This paper presents an 8-channel biomedical data acquisition ASIC achieving 108dB of dynamic range (DR). Each channel includes a 13bit DAC to compensate differential input offset of up to ±300mV, preventing saturation of the high-gain instrumentation amplifier. Chopper stabilization and DAC-noise low-pass filtering lead to an input-referred noise of 0.8μVRMS. Data processing algorithms, implemented on an FPGA, are employed to remove artefacts due to sudden DAC-switching and to cancel 50/60Hz mains interference including its harmonics. The chip is fabricated in 130nm CMOS, occupying an active area of 2.2mm2 and consuming 15mW from 1.2V and 3.3V supplies.

Real-Time biosignal classification in power-constrained embedded applications is a key step in designing portable e-healtb devices requiring hardware integration along with concurrent signal processing. This paper presents an application based on a novel biomedical System-On-Chip (SoC) for signal acquisition and processing combining a homogeneous multi-core cluster with a versatile bio-potential front-end. The presented implementation acquires raw EMG signals from 3 passive gel-electrodes and classifies 3 hand gestures using a Support Vector Machine (SVM) pattern recognition algorithm. Performance matches state-of-The-Art high-end systems both in terms of recognition accuracy (>85%) and of real-Time execution (gesture recognition time ≪300 ms). The power consumption of the employed biomedical SoC is below 10 mW, outperforming implementations on conunercial MCUs by a factor of 10, ensuring a battery life of up to 160 hours with a common Li-ion 1600 mAh battery.

Neurological disorders are a major cause of disability and mortality worldwide. Today, new devices and techniques allow clinicians and scientists to assess the living brain, monitor and alter the nervous system activity in real time. An essential approach relies on direct, physical interfacing of electrical probes with the neural tissue. Currently approved clinical interfaces have limited precision for both recording and stimulation, in large part because of their formfactor and low number of electrical channels communicating with the neural tissue. We report on current progress and remaining challenges in miniaturized, biomimetic and integrated implantable neural systems that will lead novel diagnosis, treatments and cures for people suffering and living with neurological disorders.