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Thermal scanning probe lithography (t-SPL) is a direct-write patterning method that creates high-resolution features with a heated scanning probe tip in an organic resist material. It is able to produce dense high-resolution patterns with sub-20 nm half-pitch at ambient conditions which can be transferred into silicon substrates using a hard-mask patterning stack and reactive ion etching (RIE). Feature sizes of transferred lines can be as small as 7 nm. Linear write speeds of up to 20 mm/s can be achieved. Different from e-beam lithography (EBL), in t-SPL proximity effects are absent and substrate damage of sensitive materials caused by high energy electrons is avoided. A direct inspection of the patterned area is provided during the writing process. Overlay patterning without additional alignment marks onto pre-existing structures is another feature of the t-SPL method. Existing device structures can be located precisely under a resist stack with the local probe tip and the additional target structures can then be generated with $\lt 5$ nm-precise overlay alignment. One further strength of tSPL is the capability of producing 3D patterns. The process can be controlled to produce 3D structures with $\approx 1$ nm $(1 \sigma)$ depth accuracy. Examples of unique devices fabricated by tSPL will be discussed.

An investigation of trap states at the semiconductor–oxide interface of single silicon nanowires is presented using vertical gate-all-around nanowire MOS capacitors. By performing highly accurate capacitance–voltage measurements at room temperature, the energetic distribution of interface traps $D_{{\rm it}}$ could be extracted with the quasi-static method. Although the capacitance of a single nanowire MOS capacitor with Al $_2$ O $_3$ gate oxide is only 2 fF, $D_{{\rm it}}$ values were obtained with good reproducibility. For etched, vertical Si nanowires, $D_{{\rm it}}$ in the range of $(4 \pm 1) \times 10^{12}\,\rm {cm^{-2}eV^{-1}}$ was obtained.

We have measured the thermopower and the thermal conductivity of individual silicon and indium arsenide nanowires (NWs). In this study, we evaluate a self-heating method to determine the thermal conductivity λ. Experimental validation of this method was performed on highly n-doped Si NWs with diameters ranging from 20 nm to 80 nm. The Si NWs exhibited electrical resistivity of \(\rho = (8\pm4)\, \hbox{m}\Upomega\,\hbox{cm}\) at room temperature and Seebeck coefficient of −(250 ± 100) μV/K. The thermal conductivity of Si NWs measured using the proposed method is very similar to previously reported values; e.g., for Si NWs with 50 nm diameter, λ = 23 W/(m K) was obtained. Using the same method, we investigated InAs NWs with diameter of 100 nm and resistivities of \(\rho = (25\pm5)\, \hbox{m}\Upomega\,\hbox{cm}\) at room temperature. Thermal conductivity of λ = 1.8 W/(m K) was obtained, which is about 20 to 30 times smaller than in bulk InAs. We analyzed the accuracy of the self-heating method by means of analytical and numerical solution of the one-dimensional (1-D) heat diffusion equation taking various loss channels into account. For our NWs suspended from the substrate with low-impedance contacts the relative error can be estimated to be ≤25%.

Imaging temperature fields at the nanoscale is a central challenge in various areas of science and technology. Nanoscopic hotspots, such as those observed in integrated circuits or plasmonic nanostructures, can be used to modify the local properties of matter, govern physical processes, activate chemical reactions and trigger biological mechanisms in living organisms. The development of high-resolution thermometry techniques is essential for understanding local thermal non-equilibrium processes during the operation of numerous nanoscale devices. Here we present a technique to map temperature fields using a scanning thermal microscope. Our method permits the elimination of tip–sample contact-related artefacts, a major hurdle that so far has limited the use of scanning probe microscopy for nanoscale thermometry. We map local Peltier effects at the metal–semiconductor contacts to an indium arsenide nanowire and self-heating of a metal interconnect with 7 mK and sub-10 nm spatial temperature resolution., Nature Communications, 7, ISSN:2041-1723

Frequency modulated Kelvin probe force microscopy (FM-KFM) is the method of choice for high resolution measurements of local surface potentials, yet on coarse topographic structures most researchers revert to amplitude modulated lift-mode techniques for better stability. This approach inevitably translates into lower lateral resolution and pronounced capacitive averaging of the locally measured contact potential difference. Furthermore, local changes in the strength of the electrostatic interaction between tip and surface easily lead to topography crosstalk seen in the surface potential. To take full advantage of the superior resolution of FM-KFM while maintaining robust topography feedback and minimal crosstalk, we introduce a novel FM-KFM controller based on a Kalman filter and direct demodulation of sidebands. We discuss the origin of sidebands in FM-KFM irrespective of the cantilever quality factor and how direct sideband demodulation enables robust amplitude modulated topography feedback. Finally, we demonstrate our single-scan FM-KFM technique on an active nanoelectronic device consisting of a 70 nm diameter InAs nanowire contacted by a pair of 120 nm thick electrodes., Beilstein Journal of Nanotechnology, 6, ISSN:2190-4286

Precise measurements of a complete set of thermoelectric parameters on a single indium-arsenide nanowire (NW) have been performed using highly sensitive, micro-fabricated sensing devices based on the heater/sensor principle. The devices were fabricated as micro electro-mechanical systems consisting of silicon nitride membranes structured with resistive gold heaters/sensors. Preparation, operation and characterization of the devices are described in detail. Thermal decoupling of the heater/sensor platforms has been optimized reaching thermal conductances as low as 20 nW K(-1) with a measurements sensitivity below 20 nW K(-1). The InAs NWs were characterized in terms of thermal conductance, four-probe electrical conductance and thermopower (Seebeck coefficient), all measured on a single NW. The temperature dependence of the parameters determining the thermoelectric figure-of-merit of an InAs NW was acquired in the range 200-350 K featuring a minor decrease of the thermal conductivity from 2.7 W (m K)(-1) to 2.3 W (m K)(-1).

The most direct definition of a patterning process' resolution is the smallest half-pitch feature it is capable of transferring onto the substrate. Here we demonstrate that thermal Scanning Probe Lithography (t-SPL) is capable of fabricating dense line patterns in silicon and metal lift-off features at sub 20 nm feature size. The dense silicon lines were written at a half pitch of 18.3 nm to a depth of 5 nm into a 9 nm polyphthalaldehyde thermal imaging layer by t-SPL. For processing we used a three-layer stack comprising an evaporated SiO2 hardmask which is just 2-3 nm thick. The hardmask is used to amplify the pattern into a 50 nm thick polymeric transfer layer. The transfer layer subsequently serves as an etch mask for transfer into silicon to a nominal depth of 60 nm. The line edge roughness (3 sigma) was evaluated to be less than 3 nm both in the transfer layer and in silicon. We also demonstrate that a similar three-layer stack can be used for metal lift-off of high resolution patterns. A device application is demonstrated by fabricating 50 nm half pitch dense nickel contacts to an InAs nanowire., Comment: 7 pages, 5 figures, to be published in JVST B

We have investigated the electrical and thermoelectrical properties of 30-nm-thick InAs nanowires in a temperature range between T = 200 K and T = 350 K. Devices were fabricated that allow the measurement of the conductivity and Seebeck coefficient upon the application of a gate voltage. The carrier concentration in the NWs could be varied by two orders of magnitude. The dependence of the Seebeck coefficients measured on the carrier concentration is similar to bulk InAs. A temperature-dependent mobility of IL = 1200–1400 cm 2IV s of these unpassivated NWs could be determined from both the transistor characteristics and Seebeck coefficient measurements.

Self heating degrades the performance of devices for logic storage and energy conversion. Reduced thermal conductance in nano structures has become a limiting factor towards increasing density performance and reliability of many scaled devices. CMOS and post CMOS transistors in particular exhibit a multitude of low dimensional structures and numerous interfaces making thermal design necessary [1]. In these devices heat generated in the channel and drain regions needs to be dissipated across interfaces between various materials. Other devices however may even benefit from the reduced thermal conductance of nanostructures for example in nanostructured thermoelectric energy converters or thermally assisted switching in various data storage schemes. The technological need for characterization of scaled nano devices is not paralleled with the availability of methods to measure heat flux and temperature on small scales. To measure local temperature and conductance variation we therefore focus on developing measurement tools. These are based on (A) scanning a thermometer across the sample surface region of interest so called scanning thermal microscopy (SThM) (B) measuring thermal properties directly through self heating and (C) measuring directly the heat flux through 1D structures.

The density of interface states, D it , is important for the device performance in view of the fact that it limits the inverse subthreshold slope in both, MOSFETs and TFETs [1]. This poses particular challenges for nanowire (NW) devices, because the measured D it is expected to increase due to the extensive processing and the various crystallographic orientations of the surface, which differ from the ideal (100) orientation. For a detailed investigation of the D it of NWs it is best to analyze single NW MOS capacitors. However, the capacitance of a single NW MOS capacitor lies in the fF regime which is very challenging to measure. To date, very few capacitance measurements on single NWs have been reported, e.g., on lateral devices based on InAs [2], Ge [3], and Si [4]. D it analysis of NWs has been demonstrated, however, based on capacitance measurements only of large arrays of InAs NWs [5]. In the present work, we report on the capacitance measurement and D it analysis of vertical silicon MOS capacitors based on single NWs.

In this work, we investigate high-mobility two-dimensional electron gases in AlxGa1-xAs heterostructures by employing Schottky-gate-dependent measurements of the samples' electron density and mobility. Surprisingly, we found that two different sample configurations can be set in situ with mobilities differing by a factor of more than two in a wide range of densities. This observation is discussed in the context of charge redistributions between the doping layers and is relevant for the design of future gateable high-mobility electron gases., New Journal of Physics, 12, ISSN:1367-2630

A method for determining charge carrier concentration, mobility, and relaxation time in semiconducting nanowires is presented. The method is based on measuring both the electrical conductivity and the Seebeck coefficient of the nanowire. With knowledge on the bandstructure of the material, Fermi level and charge carrier concentration can be deduced from the Seebeck coefficient. The ratio of measured conductivity and inferred charge carrier concentration then leads to the mobility, and using the Fermi level dependence of mobility one can finally obtain the relaxation time. Using this approach we exemplarily analyze the characteristics of an n-type InAs nanowire.

Integration of magnetic impurities into semiconductor materials is an essential ingredient for the development of spintronic devices such as dilute magnetic semiconductors. While successful growth of ferromagnetic semiconductors was reported for III-V and II-VI compounds, efforts to build devices with silicon technology were hampered by segregation and clustering of magnetic impurities such as manganese (Mn). Here, we report on a surface-based integration of Mn atoms into a silicon host. Control of Mn diffusion and low-temperature silicon epitaxy lead to confined Mn d-layers with low interface trap densities, potentially opening the door for a new class of spintronic devices in silicon.

We report on in situ doping of InAs nanowires grown by metal-organic vapor-phase epitaxy without any catalyst particles. The effects of various dopant precursors (Si(2)H(6), H(2)S, DETe, CBr(4)) on the nanowire morphology and the axial and radial growth rates are investigated to select dopants that enable control of the conductivity in a broad range and that concomitantly lead to favorable nanowire growth. In addition, the resistivity of individual wires was measured for different gas-phase concentrations of the dopants selected, and the doping density and mobility were extracted. We find that by using Si(2)H(6) axially and radially uniform doping densities up to 7 × 10(19) cm(-3) can be obtained without affecting the morphology or growth rates. For sulfur-doped InAs nanowires, we find that the distribution coefficient depends on the growth conditions, making S doping more difficult to control than Si doping. Moreover, above a critical sulfur gas-phase concentration, compensation takes place, limiting the maximum doping level to 2 × 10(19) cm(-3). Finally, we extract the specific contact resistivity as a function of doping concentration for Ti and Ni contacts.

Hot spots with dimensions of only a few nanometers form in numerous nanoelectronic devices. Based on recent advances in spatial resolution, these hotspots can now be studied by means of Scanning Thermal Microscopy (SThM). Here, we discuss SThM for nanoscale thermometry in comparison with other established thermometry techniques. In situ measurements of semiconductor channels for logic, and phase change memory devices are used to demonstrate today's measurement capabilities. Temperature fields characterize not only energy dissipation in in-tact devices but can also serve to identify device failure and fabrication issues.