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For radio frequency (RF) wireless integrated circuits and devices fabricated on silicon-on-insulator technologies, there has been indirect evidence of the presence of a parasitic native inversion layer, due to an effective trapped charge, “Q+,” at the interface of the buried oxide (BOX) and the underlying high resistivity p-type Si substrate in production level wafers. This inversion layer can have adverse implications for the RF performance of active devices fabricated for use in wireless technologies, notably the “RF switch.” In this study, the authors characterize the complementary-metal-oxide-semiconductor field effect RF transistor used in such a switch. The FET is built on the active epitaxial silicon layer on top of the BOX layer; its purpose is to control input and output RF signals in integrated wireless circuitry. Using scanning surface photovoltage microscopy, the authors present the first data to show quantitatively the extent of this inversion layer into the substrate. They also present device electrical performance data proving the effectiveness of the processes used to suppress the effects of Q+.For radio frequency (RF) wireless integrated circuits and devices fabricated on silicon-on-insulator technologies, there has been indirect evidence of the presence of a parasitic native inversion layer, due to an effective trapped charge, “Q+,” at the interface of the buried oxide (BOX) and the underlying high resistivity p-type Si substrate in production level wafers. This inversion layer can have adverse implications for the RF performance of active devices fabricated for use in wireless technologies, notably the “RF switch.” In this study, the authors characterize the complementary-metal-oxide-semiconductor field effect RF transistor used in such a switch. The FET is built on the active epitaxial silicon layer on top of the BOX layer; its purpose is to control input and output RF signals in integrated wireless circuitry. Using scanning surface photovoltage microscopy, the authors present the first data to show quantitatively the extent of this inversion layer into the substrate. They also present devic...

In this paper, we discuss a novel technique to reduce base resistance (R b ) and collector-base capacitance (C cb ) for higher F max in high-speed SiGe HBTs. In order to reduce C cb , we first located the origins of the different components of C cb through AC extraction. Then we utilized scanning capacitance measurements (SCM) to examine the shape of the collector-base depletion. We then propose a method to reduce the extrinsic C cb , namely by using reticle enhancement techniques to print a blocking oxide layer to inhibit boron outdiffusion. An additional benefit was the reduction of R b by reducing the base link resistance.

The use of scanning kelvin probe microscopy (SKPM) for analyzing two-dimensional dopant profiles on production-level silicon CMOS devices is described, with images of topography and dopant profiles presented. Both plan-view and crosssectional analyses are performed to measure CMOS device effective channel length (Leff), source-drain and well-junction depths. SKPM data not only tracked variations in Leff but uncovered anomalies in dopant that were responsible for device failure. For example, a nonfunctional ring-oscillator in a 0.25μm technology was debugged with SKPM. Details of sample preparation and the fabrication of durable, highly conductive (silicided) silicon kelvin probe tips which are key to acquiring reproducible, consistent data is also given.