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This paper proposes an adaptive complex coefficient filtered (CCF) full order extended state observer (ESO) type three phase enhanced phase locked loop (EPLL), which is employed in matrix reactance frequency converter (MRFC) for rotating vectors measurement estimation. EPLL phase detector was analysed first to track not only the rad frequency and transient phase, but also the amplitude of the rotating vectors. Full order ESO can filter out more high frequency disturbance, so it can track frequency and phase more accurately than proportion and integration algorithm. CCF modules were analysed in theory to attenuate the disturbance within two times of the EPLL's cut‐off frequency. The whole adaptive CCF‐ESO‐EPLL design, including stability and parameter tuning were then interpreted. The proposed CCF‐ESO‐EPLL adapts the estimated frequency with CCF to attenuate the MRFC switching non‐linear disturbance as well as unknown disturbance by the full order ESO. The MRFC topology necessary measured vectors, as well as the input side reactive power adjustment capacity, were discussed. The theoretical conclusion has been verified on a MRFC prototype. The proposed CCF‐ESO‐EPLL has less parameter tuning, less computation resource requirement, better steady and dynamic performance, and outstanding disturbance robustness. [ABSTRACT FROM AUTHOR]

A discrete‐time full‐order sensorless control strategy for high‐speed interior permanent magnet synchronous motor (IPMSM) used in electric vehicle (EV) traction system is designed in this paper. While most speed and position observer (SPO) methods are developed in the continuous‐time domain, the presence of a unit‐time‐delay block existed in feedback loop and discretisation of the algorithm can lead to performance degradation during digital implementation. In this work, speed and angle are observed using the discrete‐time four‐order IPMSM model. A quadrature phase‐locked loop model with compensation is introduced, and its stability condition is established for the first time. Furthermore, to address the potential for sudden speed changes in vehicle applications, the parameter range is further refined to keep the estimation error within a specified range. The sliding mode observer is discretised and its stability is analysed using discrete Lyapunov theory. Additionally, the time sequence of interactive signals between SPO and field‐oriented control is thoroughly examined to ensure accurate time cycle. Finally, the proposed control strategy is validated and demonstrated through bench tests and real EV (LS6 of IM Motors) tests with a 190 kW IPMSM, which can improve the accuracy by 0.3 radians at 8000 rpm compared to traditional methods, and achieve stable control at 15,000 rpm on the test bench and at 120 kph with the EV. [ABSTRACT FROM AUTHOR]

Synchronous stability is crucial for the safety and operation of AC power systems. However, most of the current researches focused on the stability of grid‐connected converters, and that of renewable equipment still lacked. In this article, the impact of the additional inertia control (AIC) on the permanent magnet synchronous generator (PMSG) is studied. It is found that with the AIC, the machine‐side converter dynamics of the PMSG cannot be ignored, and the system dominant dynamics shifts from the electromagnetic to electromechanical timescales. This article develops a simplified model for the single‐PMSG infinite‐bus system with the AIC within the electromechanical timescale, and reveals the transient synchronization stability mechanism from three aspects: the machine‐network interface, transient dominant variable, and interaction between the synchronization loop and the power imbalance loop. Finally, this article analyzes the swing characteristics of the PMSG system, and uncovers the relationship between the energy transmission and synchronization. These findings are supported by wide experimental verification and can provide the deeper physical insight and theoretical basis for the transient synchronous stability analysis of renewable‐dominated new‐type power systems. [ABSTRACT FROM AUTHOR]

In view of the cost and reliability issues caused by mechanical position sensors, position sensorless control (PSC) of permanent magnet synchronous motors (PMSMs) has received widespread attention. A series of rotor position estimation (RPE) schemes have been developed, in which the phase‐locked loop (PLL) plays an important role. However, the conventional phase‐locked loops face two thorny issues, one is the degradation of RPE performance under motor acceleration and deceleration conditions, and the other is high noise sensitivity. To this end, an adaptive gain PLL (AG‐PLL) is proposed for PSC of PMSM drives. The gains of the loop filter in the proposed AG‐PLL are adaptively adjusted with the estimation error in order to find a compromise between the estimation performance under motor acceleration and deceleration conditions and the noise sensitivity. Moreover, the proposed scheme avoids increasing the order of the PLL, so its dynamic performance is also guaranteed. The proposed scheme is tested based on the hardware‐in‐the‐loop platform. [ABSTRACT FROM AUTHOR]

Abstract A discrete‐time full‐order sensorless control strategy for high‐speed interior permanent magnet synchronous motor (IPMSM) used in electric vehicle (EV) traction system is designed in this paper. While most speed and position observer (SPO) methods are developed in the continuous‐time domain, the presence of a unit‐time‐delay block existed in feedback loop and discretisation of the algorithm can lead to performance degradation during digital implementation. In this work, speed and angle are observed using the discrete‐time four‐order IPMSM model. A quadrature phase‐locked loop model with compensation is introduced, and its stability condition is established for the first time. Furthermore, to address the potential for sudden speed changes in vehicle applications, the parameter range is further refined to keep the estimation error within a specified range. The sliding mode observer is discretised and its stability is analysed using discrete Lyapunov theory. Additionally, the time sequence of interactive signals between SPO and field‐oriented control is thoroughly examined to ensure accurate time cycle. Finally, the proposed control strategy is validated and demonstrated through bench tests and real EV (LS6 of IM Motors) tests with a 190 kW IPMSM, which can improve the accuracy by 0.3 radians at 8000 rpm compared to traditional methods, and achieve stable control at 15,000 rpm on the test bench and at 120 kph with the EV.

Abstract This paper proposes an adaptive complex coefficient filtered (CCF) full order extended state observer (ESO) type three phase enhanced phase locked loop (EPLL), which is employed in matrix reactance frequency converter (MRFC) for rotating vectors measurement estimation. EPLL phase detector was analysed first to track not only the rad frequency and transient phase, but also the amplitude of the rotating vectors. Full order ESO can filter out more high frequency disturbance, so it can track frequency and phase more accurately than proportion and integration algorithm. CCF modules were analysed in theory to attenuate the disturbance within two times of the EPLL's cut‐off frequency. The whole adaptive CCF‐ESO‐EPLL design, including stability and parameter tuning were then interpreted. The proposed CCF‐ESO‐EPLL adapts the estimated frequency with CCF to attenuate the MRFC switching non‐linear disturbance as well as unknown disturbance by the full order ESO. The MRFC topology necessary measured vectors, as well as the input side reactive power adjustment capacity, were discussed. The theoretical conclusion has been verified on a MRFC prototype. The proposed CCF‐ESO‐EPLL has less parameter tuning, less computation resource requirement, better steady and dynamic performance, and outstanding disturbance robustness.

Abstract In view of the cost and reliability issues caused by mechanical position sensors, position sensorless control (PSC) of permanent magnet synchronous motors (PMSMs) has received widespread attention. A series of rotor position estimation (RPE) schemes have been developed, in which the phase‐locked loop (PLL) plays an important role. However, the conventional phase‐locked loops face two thorny issues, one is the degradation of RPE performance under motor acceleration and deceleration conditions, and the other is high noise sensitivity. To this end, an adaptive gain PLL (AG‐PLL) is proposed for PSC of PMSM drives. The gains of the loop filter in the proposed AG‐PLL are adaptively adjusted with the estimation error in order to find a compromise between the estimation performance under motor acceleration and deceleration conditions and the noise sensitivity. Moreover, the proposed scheme avoids increasing the order of the PLL, so its dynamic performance is also guaranteed. The proposed scheme is tested based on the hardware‐in‐the‐loop platform.

Abstract Synchronous stability is crucial for the safety and operation of AC power systems. However, most of the current researches focused on the stability of grid‐connected converters, and that of renewable equipment still lacked. In this article, the impact of the additional inertia control (AIC) on the permanent magnet synchronous generator (PMSG) is studied. It is found that with the AIC, the machine‐side converter dynamics of the PMSG cannot be ignored, and the system dominant dynamics shifts from the electromagnetic to electromechanical timescales. This article develops a simplified model for the single‐PMSG infinite‐bus system with the AIC within the electromechanical timescale, and reveals the transient synchronization stability mechanism from three aspects: the machine‐network interface, transient dominant variable, and interaction between the synchronization loop and the power imbalance loop. Finally, this article analyzes the swing characteristics of the PMSG system, and uncovers the relationship between the energy transmission and synchronization. These findings are supported by wide experimental verification and can provide the deeper physical insight and theoretical basis for the transient synchronous stability analysis of renewable‐dominated new‐type power systems.

The lock-in amplifier (LIA) instruments are designed to provide signal conditioning for precision measurement systems to extract signals from extremely noisy environments. The digital LIAs design often requires a verification process to ensure hardware performance. Thus, hardware description language (HDL) with functional verification strategies offers a powerful tool to provide an field-programmable gate array (FPGA) integrated solution. In this letter, we propose a methodology of design and verification of all-digital LIA and an additive white Gaussian noise (AWGN) module able to measure extremely lower levels of signal-to-noise ratio (SNR) of $\approx $ ${10}^{-{15}}$ or down to −37 dB while a wide reserve of spurious-free dynamic range (SFDR) up to 90 dB on FPGA is ensured. To this end, the designed and implemented FPGA framework for quick, accurate, and comprehensive characterization of a given digital LIA is used to leverage the capabilities of the design under controllable AWGN noise patterns stimulus. [ABSTRACT FROM AUTHOR]

Copyright of Electric Power Automation Equipment / Dianli Zidonghua Shebei is the property of Electric Power Automation Equipment Press and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents a new structure of an Orthogonal Signal Generator for a Phase Locked Loop (OSG-PLL), utilizing an Adaptive Notch Filter (ANF) in bandwidth as the foundation. The ANF employed to generate the orthogonal system within the Phase Locked Loop (PLL), is implemented from the parallel configuration of several Bandpass Filters (BPF), starting from a lattice-structured AllPass Filter (APF). This approach offers benefits such as simplicity and reduced sensitivity to coefficient rounding in fixed-point Digital Signal Processor (DSP) implementations. The bandwidth changes adaptively by adjusting and achieving the optimization of the filter coefficients. Two adaptation algorithms are proposed, studied, and analyzed, one utilizing Gradient Descent (GD) and another based on Proportional Control of Maximum Error (ME). A series of comparative simulations are conducted using MATLAB software to validate the most effective method among the two described algorithms. The simulation results from MATLAB and the experimental results from a fixedpoint digital signal processor (DSP), specifically the TMS320F812, are showcased and examined to assess the effectiveness of the algorithm of proportional control of the ME, which has been selected as the superior alternative, thereby supporting its theoretical development. [ABSTRACT FROM AUTHOR]

The application and uses of drones in all areas are continuously rising, especially in civilian use cases. This increasing threat requires reliable drone surveillance in urban environments. Radar is the obvious candidate with its ability to detect small objects at range, in all weather conditions. The use of an L‐band networked radar for urban sensing of S‐UAS targets is explored. Small echoes from S‐UAS places a premium on synchronisation, which is the fundamental key for high performance networked radar. The effect of timing errors on the operation of the network radar is investigated theoretically and experimentally, and the processing tools for synchronising data based on the direct signal returns of the transmitter are developed. Also, drone detection using bistatic L‐band staring radar is achieved both in simulation and then in real field trials where the SNR and detection performance are computed and analysed. The updated direct signal synchronisation method for bistatic staring radar is shown to provide comparable SNR and positional accuracy for S‐UAS targets as the monostatic staring radar. [ABSTRACT FROM AUTHOR]

Copyright of Electric Power Automation Equipment / Dianli Zidonghua Shebei is the property of Electric Power Automation Equipment Press and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Fast settling phase locked loops (PLLs) play a pivotal role in many applications requiring rapid attainment of a stable frequency and phase. In modern communication standards, these PLLs are extensively utilized to guarantee precise compliance with dynamic resource allocation requirements. In processors, these PLLs manage dynamic voltage frequency scaling. Moreover, the fast-settling PLLs expedite the scanning of frequency spectra in sophisticated electronic radar set-ups, proving particularly advantageous for imaging and scanning radar applications. The rapid response exhibited by these PLLs is also harnessed in quantum technologies, catering to the urgent need for precise frequency adjustments to manipulate qubit states effectively. The strategies employed to attain fast-settling PLLs are primarily classified into five broad techniques in this article: enhanced phase frequency detection, hybrid multiple subsystems, VCO start-up, gear shift, and look-up table or finite state machine. This article explores the fundamental operational principles encompassing these techniques and presents optimal settling times for each method reported in the literature. Finally, the architectures utilizing these techniques will be evaluated based on their figure of merit (FoM), settling time, and tuning range. [ABSTRACT FROM AUTHOR]

Abstract Sub‐synchronous oscillation of grid‐connected voltage source converter (VSC) dominated by phase locked loop (PLL) is an important stability issue in nowadays power systems. The complex torque coefficient method has been used to investigate the issue because of its advantage of giving insights into source of damping and contributions of different components on damping. However, it is found that the classic complex torque coefficient method is not entirely applicable for stability analysis of VSC because of the proportional term in PLL. This paper proposes a corrected complex torque coefficient method and defines synchronous and damping coefficients. Based on the proposed method, a small‐signal stability criterion is obtained, in which the system stability depends on the sign of corrected damping coefficient. The impacts of different elements on system damping can be quantitatively evaluated through the method. It is drawn that current control loop and line dynamics contribute negative damping, whereas power control loop contributes positive damping. Moreover, the impacts of operating conditions and controller parameters on damping of different elements are analysed. The eigenvalue analyses and electromagnetic transient simulations have verified the theoretical analysis.

This research analyzes the mutual self-organized synchronization of phase-locked loops (PLLs) in the presence of variations in the free-running frequency of a PLL. In contrast to traditional synchronization methods that rely on a reference signal, this study investigates the synchronization dynamics that arise solely from the interactions of PLL nodes within a network. Previous research has proposed theoretical frameworks that can predict the synchronized states of such designs. However, these frameworks do not account for the dynamic behavior that occurs during initial synchronization. To address this gap, this work proposes a constraint that refines the understanding of initial synchronization. The results of this analysis show that there is a maximum detuning between free-running frequencies up to which synchronization is possible. Furthermore, this analysis indicates that detuning not only affects the range of time delays at which stable synchronized states emerge between PLL nodes, but also limits the allowable range of initial phase differences for stable synchronization. In the cases studied, a frequency difference of 1.56% reduces the probability of achieving stable synchronized states through self-organized synchronization to 73.5%, while no stable synchronization can be achieved at a frequency difference greater than 2.65%. The study underscores the critical importance of operating ranges when implementing mutual coupling. In particular, all PLL nodes must have overlapping lock ranges to achieve stable synchronization. It also emphasizes the need for accurate analysis of hold and lock ranges in relation to the time delays between coupled PLL nodes.

Abstract The phase‐locked loop (PLL) is a critical control module applied in the control system of renewable energy sources (RESs) to synchronize with the grid voltage. When a fault occurs, the dynamic response process of the PLL will generate a phase locking error, resulting in a mass of harmonic components in the fault current of the PV inverter, which further poses challenges to transformer differential protection. To address the challenges posed by the phase locking error in practical engineering applications, this paper proposes an improved scheme that uses a digital computer algorithm to record and store the pre‐fault voltage and introduces the limiting coefficient. Firstly, the memory voltage is used to eliminate the phase locking error of the PLL, thereby mitigating harmonic distortion in the fault current of the RESs and ensuring the reliability of the transformer differential protection. In addition, the limiting coefficient is introduced to eliminate the effect of the increased amplitude of the fault current caused by the memory voltage. The voltage reference value of the inverter is multiplied by an appropriate limiting coefficient k and then output to the physical system. Finally, the effectiveness of the proposed scheme is verified by MATLAB/Simulink simulation.

Copyright of Electric Machines & Control / Dianji Yu Kongzhi Xuebao is the property of Electric Machines & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Sub‐synchronous oscillation of grid‐connected voltage source converter (VSC) dominated by phase locked loop (PLL) is an important stability issue in nowadays power systems. The complex torque coefficient method has been used to investigate the issue because of its advantage of giving insights into source of damping and contributions of different components on damping. However, it is found that the classic complex torque coefficient method is not entirely applicable for stability analysis of VSC because of the proportional term in PLL. This paper proposes a corrected complex torque coefficient method and defines synchronous and damping coefficients. Based on the proposed method, a small‐signal stability criterion is obtained, in which the system stability depends on the sign of corrected damping coefficient. The impacts of different elements on system damping can be quantitatively evaluated through the method. It is drawn that current control loop and line dynamics contribute negative damping, whereas power control loop contributes positive damping. Moreover, the impacts of operating conditions and controller parameters on damping of different elements are analysed. The eigenvalue analyses and electromagnetic transient simulations have verified the theoretical analysis. [ABSTRACT FROM AUTHOR]

The phase‐locked loop (PLL) is a critical control module applied in the control system of renewable energy sources (RESs) to synchronize with the grid voltage. When a fault occurs, the dynamic response process of the PLL will generate a phase locking error, resulting in a mass of harmonic components in the fault current of the PV inverter, which further poses challenges to transformer differential protection. To address the challenges posed by the phase locking error in practical engineering applications, this paper proposes an improved scheme that uses a digital computer algorithm to record and store the pre‐fault voltage and introduces the limiting coefficient. Firstly, the memory voltage is used to eliminate the phase locking error of the PLL, thereby mitigating harmonic distortion in the fault current of the RESs and ensuring the reliability of the transformer differential protection. In addition, the limiting coefficient is introduced to eliminate the effect of the increased amplitude of the fault current caused by the memory voltage. The voltage reference value of the inverter is multiplied by an appropriate limiting coefficient k and then output to the physical system. Finally, the effectiveness of the proposed scheme is verified by MATLAB/Simulink simulation. [ABSTRACT FROM AUTHOR]

Abstract In order to attenuate the oscillations on the estimated frequency of a phase‐locked loop (PLL), the effective suppression of low‐order harmonics in grid voltage is a crucial issue in three‐phase grid‐connected inverters, which use the standard PLL based on a double second‐order generalized integrator (DSOGI‐PLL). Analysis shows that the SOGI module exerts a stronger filtering effect in generating the quadrature signal than the in‐phase signal. In this context, two novel cascaded SOGI module filtering structures have been developed, based on which the PLLs are proposed. In comparison to the previously proposed method for addressing the problem of input voltage harmonics, the proposed method has stronger filtering ability and can flexibly select the levels of SOGI module cascading based on the degree of grid voltage distortion to achieve a balance between system dynamic performance and filtering performance. The proposed PLLs' approximation small signal model is established, and the method for designing the system control parameters is also provided. In the case of frequency steps, phase angle jumps, harmonic injection, and unbalanced voltage sag, Matlab modelling and experimental results demonstrate that the proposed PLLs can efficiently extract the frequency and phase of the fundamental positive sequence component and behave better in steady‐state and dynamic performance.

Abstract This paper proposes a new robust method for accurately and reliably estimating remote bus frequencies in a power system. Two different measurement sources for the remote bus frequency are considered, that is, the ideal Frequency Divider (FD) and the Synchronous Reference Frame Phase Locked Loops (SRF‐PLLs). Each measurement signal encounters different uncertainties and data quality issues. In this paper, both data sources are employed and fused together to better estimate the remote bus frequencies. To this end, the model structure of the power system is selected and an Unscented Kalman Filter (UKF) is utilized together with a fusion covariance intersection method to enhance the accuracy of the estimated bus frequency. Since the fusion estimation method fails in case of quality issues on both channels, a robust Generalized Maximum‐likelihood UKF (GM‐UKF) using a novel outlier detection criteria is developed. The impact of the resulting robust fusion filter on the estimation of the remote bus frequencies and on the performance of WAPSS, which makes use of the estimated frequencies as the feedback signal, is examined via simulations. The results demonstrate the excellent performance and reliability of the proposed method in dealing with noise filtering and outlier suppression while ensuring a high statistical efficiency.

Abstract In this paper, an integral‐type half‐tangent phase‐locked loop (IHTan‐PLL) is proposed for the varying‐frequency AC grids of more electric aircraft (MEA). First, the performance of the synchronous reference frame phase‐locked loop (SRF‐PLL) and half‐tangent phase‐locked loop (HTan‐PLL) is discussed from a large‐signal viewpoint. When the frequency changes largely, the SRF‐PLL has many oscillations and endures a rather long transient process. The HTan‐PLL can address the large frequency jumps. However, for the varying‐frequency AC grids with harmonic disturbances, the HTan‐PLL still has oscillations in estimating the frequency when the frequency jumps largely. To enhance the performance of the SRF‐PLL and HTan‐PLL, the IHTan‐PLL is developed for the varying‐frequency AC grids with harmonic disturbances. The IHTan‐PLL performs better than the SRF‐PLL and HTan‐PLL in addressing the large frequency jumps. Specifically, under any large frequency changes, the IHTan‐PLL still converges to the equilibrium point (0,0), and no oscillations emerge. In addition, the IHTan‐PLL has better steady‐state accuracy in estimating the frequency than the SRF‐PLL and HTan‐PLL. The experimental results also demonstrate the superior performance of the proposed IHTan‐PLL.

This paper proposes an improved version of Synchronous Reference Frame (SRF) based phase locked loop (PLL). The conventional SRF-PLL structure is modified and made adaptive using a Least Means Square (LMS) algorithm. The benefit of the proposed scheme is that the tuning of proportional controller (PI) gain parameters can be achieved automatically without having to optimise these parameters manually. The PLL is utilised to track important electrical grid parameters such as phase angle, unit synchronisation templates and voltage magnitude. This performance study investigates several cases such as voltage sag/swell, wide frequency deviation, phase jump, presence of noise and harmonics in the supply voltage. The impact of constant and adaptive PI parameters influencing PLL performance is investigated. Finally, a fair comparison is presented which discusses the proposed adaptive SRF-PLL(ASRF-PLL), conventional fixed gain SRF-PLL, unit template-based synchronisation technique and Delayed Signal Cancellation based PLL (DSC-PLL). [ABSTRACT FROM AUTHOR]

This paper proposes a new robust method for accurately and reliably estimating remote bus frequencies in a power system. Two different measurement sources for the remote bus frequency are considered, that is, the ideal Frequency Divider (FD) and the Synchronous Reference Frame Phase Locked Loops (SRF‐PLLs). Each measurement signal encounters different uncertainties and data quality issues. In this paper, both data sources are employed and fused together to better estimate the remote bus frequencies. To this end, the model structure of the power system is selected and an Unscented Kalman Filter (UKF) is utilized together with a fusion covariance intersection method to enhance the accuracy of the estimated bus frequency. Since the fusion estimation method fails in case of quality issues on both channels, a robust Generalized Maximum‐likelihood UKF (GM‐UKF) using a novel outlier detection criteria is developed. The impact of the resulting robust fusion filter on the estimation of the remote bus frequencies and on the performance of WAPSS, which makes use of the estimated frequencies as the feedback signal, is examined via simulations. The results demonstrate the excellent performance and reliability of the proposed method in dealing with noise filtering and outlier suppression while ensuring a high statistical efficiency. [ABSTRACT FROM AUTHOR]

Copyright of Electric Power Automation Equipment / Dianli Zidonghua Shebei is the property of Electric Power Automation Equipment Press and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Electric Power Automation Equipment / Dianli Zidonghua Shebei is the property of Electric Power Automation Equipment Press and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Electric Power Automation Equipment / Dianli Zidonghua Shebei is the property of Electric Power Automation Equipment Press and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, an integral‐type half‐tangent phase‐locked loop (IHTan‐PLL) is proposed for the varying‐frequency AC grids of more electric aircraft (MEA). First, the performance of the synchronous reference frame phase‐locked loop (SRF‐PLL) and half‐tangent phase‐locked loop (HTan‐PLL) is discussed from a large‐signal viewpoint. When the frequency changes largely, the SRF‐PLL has many oscillations and endures a rather long transient process. The HTan‐PLL can address the large frequency jumps. However, for the varying‐frequency AC grids with harmonic disturbances, the HTan‐PLL still has oscillations in estimating the frequency when the frequency jumps largely. To enhance the performance of the SRF‐PLL and HTan‐PLL, the IHTan‐PLL is developed for the varying‐frequency AC grids with harmonic disturbances. The IHTan‐PLL performs better than the SRF‐PLL and HTan‐PLL in addressing the large frequency jumps. Specifically, under any large frequency changes, the IHTan‐PLL still converges to the equilibrium point (0,0), and no oscillations emerge. In addition, the IHTan‐PLL has better steady‐state accuracy in estimating the frequency than the SRF‐PLL and HTan‐PLL. The experimental results also demonstrate the superior performance of the proposed IHTan‐PLL. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive sliding mode observer (ASMO) associated with a phase locked loop (PLL) is assessed for the sensor‐less control of a rotor‐tied doubly‐fed induction generator (RDFIG). In the proposed PLL‐ASMO estimator, the ASMO utilizes the stator current, the stator voltage, and the back electromotive force (EMF) as state variables. The proposed ASMO is used in order to estimate the back‐EMF from which the slip position/speed is extracted using a PLL. The design of the ASMO gains is based on the Lyapunov stability criteria to ensure the convergence of the proposed observer in a finite time. Therefore, the main contribution of this paper is to propose a PLL‐based ASMO estimator that aims to improve the estimation by reducing the chattering effect. A comparative study between the standard PLL‐SMO estimator and the PLL‐ASMO estimator is presented. Also, For the first time, an adaptive sliding mode observer is used for the sensor‐less control of a RDFIG. The performance of the proposed sensor‐less control strategy is validated through simulation and experimental measurements under various operating conditions. Furthermore, the estimator is shown to be robust to machine parameter variation. [ABSTRACT FROM AUTHOR]

In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of a phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology is applied for the optimized design of an 8-bit dual-loop CDR, designed with the CMOS TSMC 65 nm process node. The CDR is based on an extended, in terms of phase resolution, version, with a novel PI topology proposed in this work. The proposed CDR loop has a minimum frequency offset tracking ability equal to 500ppm at 5.83 Gbps, and so is suitable for adoption either in mesochronous or plesiochronous High Speed Serial Interface (HSSI) receivers. It consumes 14.2 mW with 1 V supply voltage and is able to achieve better than 10−10 Bit Error Rate (BER) performance. The CDR loop performance verification has been realized through the AMS simulator of Analog Design Environment of Cadence, by co-simulations of the transistor level CDR circuit with the Verilog-AMS based jitter generator.

This article proposes a double-synchronous-reference-frame-based power-synchronized grid-following inverter (DS-PSGFLI). In contrast to existing types of phase-locked-loop (PLL)-based grid-following inverters (GFLIs) and PLL-less power-synchronized GFLIs (PSGFLIs), the suggested PLL-less DS-PSGFLI operates seamlessly during unbalanced grid faults in both strong and weak grid connections, while maintaining stability and avoiding oscillations. Furthermore, unlike previous control strategies for PSGFLIs that regulate terminal output power, the proposed method regulates the power at the point of common coupling (PCC). This approach aligns with common PCC control strategies in GFLIs and grid-forming inverters, thereby avoiding the impacts of voltage drop across the inverter output filter and high voltage harmonics at the inverter terminal. In the proposed DS-PSGFLI, the positive and negative sequences of the PCC voltage and current measurements are first extracted. Then, an outer power controller is employed to regulate the positive active and reactive power at the PCC to the desired references. The outer power controller generates both the positive internal angle required for grid synchronization and the positive current reference for the inner current of the positive sequence loop. When unbalanced grid faults occur, the negative sequence loop adjusts its output signals to mitigate the resulting oscillations at twice the fundamental frequency. The effectiveness of the proposed control strategy is validated through simulations and experimental tests, demonstrating its reliable performance across a wide range of test scenarios.

Abstract In this paper, an adaptive sliding mode observer (ASMO) associated with a phase locked loop (PLL) is assessed for the sensor‐less control of a rotor‐tied doubly‐fed induction generator (RDFIG). In the proposed PLL‐ASMO estimator, the ASMO utilizes the stator current, the stator voltage, and the back electromotive force (EMF) as state variables. The proposed ASMO is used in order to estimate the back‐EMF from which the slip position/speed is extracted using a PLL. The design of the ASMO gains is based on the Lyapunov stability criteria to ensure the convergence of the proposed observer in a finite time. Therefore, the main contribution of this paper is to propose a PLL‐based ASMO estimator that aims to improve the estimation by reducing the chattering effect. A comparative study between the standard PLL‐SMO estimator and the PLL‐ASMO estimator is presented. Also, For the first time, an adaptive sliding mode observer is used for the sensor‐less control of a RDFIG. The performance of the proposed sensor‐less control strategy is validated through simulation and experimental measurements under various operating conditions. Furthermore, the estimator is shown to be robust to machine parameter variation.

Abstract A low‐power wideband self‐biased phase‐locked loop (SPLL) is proposed for multi‐protocol SerDes applications in this letter. With the proposed adaptive fast‐locking current circuit (AFLCC) and self‐biased charge pump (CP), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start‐up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1‐3‐GHz SPLL, fabricated in TSMC 28‐nm CMOS process, occupies a compact 0.028 mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed at 1 GHz frequency.

The interface inverters arbitrate the network impedance based on the source characteristics for efficient solar energy harvesting. The wide impedance arbitration capability of the interface inverter defines the wide operational integrity with the ac network. In the weak grid scenario, the uncompensated grid inductance beyond point of common coupling (PCC) offers the negative damping for power oscillations at the PCC tugs the system toward instability. In this article, the negative damping influence due to interactions between the system impedance (filter inductance and grid power injection resistance) and ac network impedance (grid inductance) on the inverter closed-loop controller is characterized by observing the natural phase deviations in real and imaginary axis. Through distinguished system’s natural response, a novel second-order system impedance model is derived, and proposed current controller gain characterization aiming to achieve positive damping to mitigate the PCC’s oscillations. Further tuning of the controller based on the natural response of the derived impedance model accomplishes the enhanced grid injected power quality. The efficacy of the derived system impedance model along with coherence of current controller gain is demonstrated on hardware for enhanced power quality under the stable operating region. [ABSTRACT FROM AUTHOR]

In this article, a half-tangent phase-locked loop (HTan-PLL) is proposed for variable-frequency grids of more electric aircrafts. First, the pros and cons of the synchronous reference frame PLL (SRF-PLL) are discussed in a nonlinear framework. To address the disadvantages, a half-tangent phase detector (PD) is developed and a novel PLL is then proposed. Subsequently, a phase portrait-based analysis and a Lyapunov function-based argument are provided. It is proven that the HTan-PLL has a good performance in terms of steady-state accuracy and fast dynamics, even under large frequency changes. Compared with the conventional SRF-PLL, the proposed HTan-PLL outperforms with the following features: faster dynamics than the SRF-PLL when the frequency varies largely; no unstable equilibrium points, while the SRF-PLL has infinite unstable equilibrium points; and when the grid frequency jumps widely, the HTan-PLL converges to the unique equilibrium point (0,0). By contrast, the SRF-PLL goes to different equilibrium points. Experimental tests are provided, which verify the superior performance of the HTan-PLL. [ABSTRACT FROM AUTHOR]

In wide ac input frequency applications, such as more electric aircraft, ac input frequency of the three-phase buck rectifier varies in the range of 360–800 Hz. In this article, a reconstructed phase voltages based power following control for the three-phase buck rectifier under unbalanced input phase voltages in wide ac input frequency application is proposed. The input phase voltages are reconstructed to get more balanced modulation signals compared with the input phase voltages. The input currents are controlled to be in proportion to the reconstructed phase voltages to mitigate the imbalance of the input currents. The control strategy is simple and easy to be realized in digital. The analysis and design of the proposed control strategy and digital implementation are illustrated. An experimental prototype with 1.5 kW is built. The experimental results show that the sinusoidal input currents can be obtained when input phase voltages are unbalanced in wide ac input frequency application. [ABSTRACT FROM AUTHOR]

The phase-locked loop (PLL) will have a negative impact on the stability of doubly fed induction generators (DFIG) system under inductive weak grid. Some PLL-less methods have been presented to remove the PLL such as switching the synchronous reference frame to the virtual reference frame or αβ-frame. Based on the equivalent single-input single-output impedance model, it is found that the DFIG systems implemented in the virtual reference frame or αβ-frame are more stable than synchronous reference frame. The reason is that the stator voltage will disturb the reference current calculation of the virtual reference frame and αβ-frame, then introduce a reference calculation matrix Gcal. This matrix will keep the phase of DFIG system always −90° around fundamental frequency, then narrow the negative resistance band and enhance the phase margin (PM). In order to further illustrate the stability improvement caused by Gcal, this article proposes a stability improvement method by emulating the Gcal in synchronous reference frame, so as to improve the PM while retaining the advantages of PLL under unbalanced or harmonically distorted voltage, and fault ride through. The experimental results validate the aforementioned conclusions. [ABSTRACT FROM AUTHOR]

In this article, we aim to design a simple dc immune phase-locked loop (PLL) for single-phase applications. The dc offset is inherently rejected using only two delay operators. The dc offset in the synchronization unit is a challenging problem that causes oscillation in the estimated grid information. Using conventional filters to solve this problem is ineffective since this degrades the synchronization unit's dynamic performance. Different PLLs have been introduced in this article to mitigate the dc offset. Each has its merits and demerits, such as complex structure, high computational burden, and slow transient response. The proposed PLL incorporates two cascaded delayed signal cancellation operators with an arbitrary-length time delay, rejects the dc offset, and perfectly synchronizes with the grid. This article also presents a small-signal model to facilitate the loop filter design and stability analysis. Besides the simulations, the PLL's performance is validated experimentally under various disturbance conditions, with comparisons with other PLLs. [ABSTRACT FROM AUTHOR]

For single-phase grid-connected inverters, the second-order generalized integrator-based phase-locked loop (SOGI-PLL) is widely used for good harmonics attenuation and frequency adaptability. However, existing studies usually neglect the frequency feedback loop in the modeling and design process, and thus, the potential instability caused by the frequency feedback loop is not well explained. Besides, the improper design of SOGI-PLL can lead to the inverter instability both under ideal and weak grid conditions. Therefore, by fully considering the coupling of the frequency feedback loop, this article establishes an accurate model for SOGI-PLL. Furthermore, effects of different PLL parameters on behaviors of both the SOGI-PLL itself and the inverter are studied, based on which a graphical method for PLL parameters design is proposed. As proved, the frequency feedback loop can deteriorate the stability and performance of both SOGI-PLL itself and inverter system, especially if rapid transient is expected. The modeling method is also extended to the low-pass filter-SOGI-PLL and the improved parameters design is discussed. Experimental results verify the correctness of the proposed PLL model and the abovementioned analysis results. The proposed model is helpful to deeply reveal the instability mechanism and provides a reference for the PLL design under nonideal grid conditions. [ABSTRACT FROM AUTHOR]

This article proposes a novel sensorless control strategy for permanent magnet synchronous motor drives using reduced order quasi resonant-based extended state observer (ROQR-ESO) and Newton–Raphson method-based phase-locked loop (NRM-PLL). Due to the low-pass filtering characteristics, the conventional linear extended state observer (LESO) is not adequately able to track the fast-varying back electromotive forces (BEMFs). On this basis, the ROQR-ESO, which plants a ROQR controller into the internal model of conventional LESO, is presented to obtain BEMFs without phase lag. Moreover, the NRM-PLL, regarded as an improved finite position set-PLL, is proposed. After the rotor position is divided into four parts by utilizing a position quartering method, the extremely accurate rotor position can be obtained only by three iterations. In this method, no parameters need to be adjusted and great dynamic response can be achieved. The capacity of the proposed scheme is verified on a 750 W permanent magnet synchronous motor drive platform. [ABSTRACT FROM AUTHOR]

Abstract A novel frequency‐to‐voltage converter based phase‐locked loop (PLL) is proposed to overcome the inability of a frequency‐to‐voltage converter based frequency‐locked loop to lock phase. The proposed dual‐loop PLL adds variable phase‐locking capability, such that the phase locking angle can vary from 0–360°. The additional variable phase‐locking can be applied in data communication in the form of phase modulation. The design is targeted for a 0.5‐μm CMOS process. The proposed design generates a 480 MHz clock from a reference clock of 15 MHz. In simulation, the proposed PLL locks within 3.56 μs while consuming 1.61 mW of power.

Coordinated and efficient operation in large, complex systems requires the synchronization of the rhythms of spatially distributed components. Such systems are the basis for critical infrastructure such as satellite navigation, mobile communications, and services like the precision time protocol and Universal Coordinated Time. Different concepts for the synchronization of oscillator networks have been proposed, in particular mutual synchronization without and hierarchical synchronization from a reference clock. Established network synchronization models in electrical engineering address the role of inevitable cross-coupling time delays for network synchronization. Mutual synchronization has been studied using linear approximations of the coupling functions of these models. We review previous work and present a general model in which we study synchronization taking into account nonlinearities and finite time delays. As a result, dynamical phenomena in networks of coupled electronic oscillators induced by time delays, such as the multistability and stabilization of synchronized states can be predicted and observed. We study the linear stability of nonlinear states and predict for which system parameters synchronized states can be stable. We use these results to discuss the implementation of mutual synchronization for complex system architectures. A key finding is that mutual synchronization can result in stable in- and anti-phase synchronized states in the presence of large time delays. We provide the condition for which such synchronized states are guaranteed to be stable.

Abstract Low earth orbit (LEO) constellations for enhancing global navigation satellite systems (GNSS) have been investigated and studied due to their higher floor power and rapid geometric changes. Compared with GNSS based on medium orbit (MEO) and geostationary (GEO) satellites, the higher Doppler frequency is one of the problems faced by the LEO enhanced GNSS. For the traditional BPSK signal, the complexity has been greatly improved in acquisition, especially in the cold start state, which means more requests on the signal design. The periodic chirp signal modulated by the pseudo‐noise code (chirp‐PC) is proposed as the ranging signal of LEO enhanced GNSS. The coupling characteristic of Doppler and delay in chirp‐PC can make the search frequency grid less than the traditional BPSK signal with the same acquisition performance, which can greatly reduce the complexity. However, the delay estimation obtained by the acquisition is biased. A tracking loop based on the chirp phase locked loop (CPLL) was proposed for removing the coupling of Doppler and time delay. The simulations show that the tracking loop can track chirp‐PC signals stably and unbiasedly, and the tracking accuracy is similar to that of the corresponding BPSK signal. Therefore, the chirp‐PC signal is a new choice for LEO enhanced GNSS with low acquisition complexity and equivalent tracking accuracy to BPSK.

A low‐power wideband self‐biased phase‐locked loop (SPLL) is proposed for multi‐protocol SerDes applications in this letter. With the proposed adaptive fast‐locking current circuit (AFLCC) and self‐biased charge pump (CP), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start‐up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1‐3‐GHz SPLL, fabricated in TSMC 28‐nm CMOS process, occupies a compact 0.028 mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed at 1 GHz frequency. [ABSTRACT FROM AUTHOR]

MEMS resonant accelerometers are robust to electromagnetic interference and have higher sensitivity and resolution. However, they are susceptible to temperature variation, which may limit this type of sensor used in high-end applications. This paper proposes a TDS-PLL with MEMS VCO for MEMS resonant accelerometers to be immune to temperature drift. The theoretical analysis of TDS-PLL MRA demonstrates it can suppress the temperature drift, which is verified by simulation and measurement results. Measurement results of the TDS-PLL MRA show that the bias instability is $13.15~\mu \text{g}$ and the noise level is $7.04~\mu \text{g}/\surd $ Hz with 0.32g full scale at room temperature. The temperature coefficient of bias stability in TDS-PLL MRA achieves 2.21 mg/°C in a temperature range of 300K to 360K, which is lower 5.5 times than that of the traditional PLL MRA with frequency shift. [2022-0098] [ABSTRACT FROM AUTHOR]

Sensorless drives of interior permanent magnet synchronous motors (IPMSMs) find a broad range of applications due to their inherent benefits. In practical electrified propulsions, the IPMSM drives are usually working in highly utilized conditions where the performance and stability could deteriorate. Without considerable compensation, this vulnerability causes the existing phase-locked loops (PLLs), estimators, or observers to lose the synchronization with the rotor position. To achieve better performance and reduce the estimation error, in a PLL-type framework for sensorless control, a position error observer (PEO) utilizing the current errors as correction terms plays the role of the phase detector. A reduced-order extended state observer (ESO) is presented to form the loop filter with a switched nonsmooth feedback structure. The outstanding property of the PEO and nonsmooth ESO is verified through experiments. The results demonstrate its strong adaptability for model uncertainties and disturbances along with the quick convergence speed and minimal oscillation. [ABSTRACT FROM AUTHOR]

To cope with the weak grid stability issue of grid-tied voltage source converters (VSCs), this article proposes an artificial neural network (ANN) based approach for online stabilization control of the grid-tied VSC with the pole-tracking feature. First, an ANN is adopted to establish the mapping between the control parameters and the closed-loop poles of the grid-VSC system, serving as a computationally light model surrogate that is favorable for real-time control applications. Then, an online parameter search algorithm enabling simultaneous tuning of multiple controllers and parameters is developed, by which the system's poles under a new grid condition can be pulled to the reference ones, i.e., achieving the pole-tracking-based stabilization control of this article. Finally, the efficacy of the proposed method along with its stabilization effect is verified by MATLAB simulations and experimental results. [ABSTRACT FROM AUTHOR]

Under grid distortions, Modular Multilevel Converters (MMC) must adopt proper control strategies to fulfill the power system requirements and ensure a stable operation. An inappropriate control under such conditions may lead to energy unbalances between the MMC legs, inaccurate current injection, and failure in the synchronization process. In this context, sequence extraction methods play a critical role in enhancing the performance of the control, firstly, by aiding the Phase-Locked Loop (PLL) to maintain the synchronization with the AC grid by following the positive sequence fundamental component of the voltage, secondly, by allowing accurate active and reactive currents injection via the decoupled Voltage Oriented Control (dVOC), thirdly, by properly managing the internal energy of the MMC through the circulating current control. In prior researches, some sequence extraction methods have been used for MMC STATCOM. However, the sequence extraction was not the core of the performed studies and their impact on the system behavior has not been highlighted or tested in several grid conditions. This work fills this gap by first assessing the performance of a Single Delta Bridge Cell MMC (SDBC-MMC) STATCOM with four well-known sequence extraction methods (i.e., Decoupled Double Synchronous Reference Frame (DDSRF), Dual Second Order Generalized Integrator (DSOGI), Improved DSOGI, and Fortescue matrix-based (FMB) filter under normal and abnormal grid conditions, then, finding the most suitable one in terms of stability, dynamics, and functionalities. [ABSTRACT FROM AUTHOR]