Search

AIMS Our aim was to study the effectiveness of coronary stent implantation during the endovascular treatment (EVT) of acute basilar artery occlusion (BAO) with occlusion-underlying intracranial atherosclerotic stenosis (ICAS). METHODS AND RESULTS We retrospectively analysed 91 consecutive BAO patients who underwent EVT between February 2014 and January 2019 in a single, high-volume neurointerventional centre. We studied the effect of immediate coronary stent implantation on the clinical outcome of BAO with occlusion-underlying stenosis. BAO patients with underlying ICAS (n=41) were characterised by longer symptom-onset-to-reperfusion times (231 min vs 173 min, p=0.0020), lower TICI 2b-3 reperfusion rates (65.85% vs 90.00%, p=0.0084), and higher overall mortality (HR 2.021, p=0.0417) compared to the BAO cases without ICAS (n=50). The patients undergoing stenting (n=18) had lower residual basilar artery (BA) stenosis (14.7% vs 81.0%, p

Carrying out deep packet inspection (DPI) in aggregated network connections remains a continuous requirement even though the line rate reaches and exceeds 100 Gb/s. The increasing packet-arrival rate necessitates efficient solutions for on-the-fly packet parsing, packet classification, and distribution for parallelized, software-based payload inspection. Inspection complexity and real-time processing are competing requirements. The deep analysis capabilities of software-based approaches can be enhanced by hardware-based support on time-critical packet parsing and classification. Moreover, some payload inspection tasks can be carried out in hardware as well, further reducing the resources spent on software-based solutions. This paper aims at presenting the state-of-the-art and describing a set of best practices in field programmable gate arrays (FPGA)-based packet processing, which can be applied for DPI-related tasks at 100 Gb/s and beyond. Accordingly, we provide an architectural view of the DPI systems throughout the paper. Besides summarizing the limitations of hardware- and software-based solutions for the three processing phases within a DPI system (packet parsing, packet classification, and payload inspection), this paper reveals the possible trade-offs for choosing the different technical approaches. These limitations include operating frequency, bus size, available memory, on-chip physical resources for hardware-based implementations, and CPU time for software-based solutions.

The increasing number of Voice over LTE deployments and IP-based voice services raise the demand for their user-centric service quality monitoring. This domain’s leading challenge is measuring user experience quality reliably without performing subjective assessments or applying the standard full-reference objective models. While the former is time- and resource-consuming and primarily executed ad-hoc, the latter depends upon a reference source and processes the voice payload that may offend user privacy. This paper presents a packet-level measurement method (introducing a novel metric set) to objectively assess network and service quality online. It is accomplished without inspecting the voice payload and needing the reference voice sample. The proposal has three contributions: (i) our method focuses on the timeliness of the media traffic. It introduces new performance metrics that describe and measure the service’s time-domain behavior from the voice application viewpoint. (ii) Based on the proposed metrics, we also present a no-reference Quality of Experience (QoE) estimation model. (iii) Additionally, we propose a new method to identify the pace of the speech (slow or dynamic) as long as voice activity detection (VAD) is present between the endpoints. This identification supports the introduced quality model to estimate the perceived quality with higher accuracy. The performance of the proposed model is validated against a full-reference voice quality estimation model called AQuA, using real VoIP traffic (originated in assorted voice samples) in controlled transmission scenarios.

Background and purpose: Brain arteriovenous malformations (AVM) are uncommon vascular lesions with the risk of hemorrhage, epileptic seizures, neurological deficits, and headache. Comparing the risks of the natural history and that of preventive treatment, a recent study has found observation more beneficial than treatment for unruptured AVMs. This study, however, did not consider the long-term impact of carrying a brain AVM on everyday activities. In this study we analyzed the Quality Of Life (QOL) of patients with untreated AVMs, a measure increasingly used in clinical trials to asses this kind of impact.Methods: We enrolled 36 patients with unruptured, untreated brain AVM from our hospital database and measured their QOL retrospectively using the EQ-5D-5L questionnaire. As a control group we used the results of the Research Report, a nationwide study based on the quality of life of 5534 healthy Hungarians in 2002. Due to the low number of cases, statistical analysis could not be made.Results: Headache proved to be the most common AVM-related sign in our cohort (40%, n = 17), with a female predominance; neurological deficit was detected in 33% (n = 14), while epileptic seizures occurred in 26% (n = 11), more commonly affecting male subjects. Anxiety and discomfort seemed to be the most prevalent influencing factors on QOL, especially in the youngest age group (18–34 years). Female subjects showed a greater dependence than men in all age groups, though males had a more significant impairment in their usual activities. Older patients were affected more significantly in their self-care and usual activities compared with the younger population.Conclusions: Untreated AVMs have a significant negative impact on patients carrying unruptured brain AVMs, as proved by QOL assessment. Beside neurological deficits, this impact should also be considered in the therapeutic decision.

The growing scale of Voice over LTE deployments as well as the wide spread of Internet voice services increase the demand for their user centric service quality monitoring. The primary question in this domain is how a provider can monitor the quality of user experience without executing subjective assessments or applying the common full reference objective quality models. While the former is time and resource consuming and typically performed ad-hoc, the latter requires a reference source, and by processing the voice data it may offend user privacy.In this paper, we introduce a novel packet-level measurement method (including a novel metric set) to measure network and service quality online. It is done without inspecting the voice payload and needing for the reference voice source. The performance of the proposed model is validated against a full reference voice quality estimation model called AQuA, using real VoIP traffic (generated from various voice samples) in controlled network scenarios.

Industrial automation systems traditionally require communication systems to have high availability, high security and low latency. This results in efficient protocols with low protocol-processing overhead, but somewhat rigid communication systems that are cumbersome to scale up when deployed. On the other hand, Internet Protocol based communication – which is often preferred by IoT systems – offer high flexibility, but best-effort reliability. Furthermore, various radio access technologies have been created for IoT devices facilitating their IP networking as well. Nevertheless, these wireless technologies are rarely capable of corresponding to the strict requirements of complex industrial use cases, they usually cannot certain the necessary Quality of Service (QoS) promises.On the contrary, 5G mobile technologies are being developed exactly for such industrial and automation IoT use cases. Certainly, there are traffic prioritization techniques available for 4G and 5G systems, but their capabilities need to be investigated for Industrial IoT feasibility, before deployment. This paper aims to provide a feasibility study for applying mobile networking technologies (4G and 5G) – and its QoS guarantees – to IIoT applications. The proposed methodology can be extended for benchmarking whether a given use case can benefit from applying mobile networking for its various industrial and automation systems.

While Distributed Denial of Service (DDoS) attacks are among the most investigated and documented cyber threats, their mitigation is still not solved. The latest generation of DDoS threats requires a different protection scheme. Current widespread Intrusion Prevention Systems (IPS) have a reaction time in the range of seconds and minutes. However, hit-and- run type of attacks, that last only a few tens or hundreds of milliseconds, are therefore often invisible for these security systems. We have developed a set of DDoS detection methods to identify the Top-9 Akamai threat types that cover more than 96% of DDoS attacks globally. As proof-of-concept (PoC), we designed and implemented a detection engine incorporating these methods in a 100 Gbps packet processing FPGA platform. The PoC system identifies the specified attacks within milliseconds. The short detection time also enables preventing hit-and-run attacks, which deliver high intensity malicious traffic over a short period of time. We have validated our system with real-life as well as synthesized DDoS attacks. The real DDoS traces were captured in a medium-sized datacenter network. In this demonstration, we are going to showcase the effectiveness of the detector engine in various security scenarios.

Timely detection and mitigation of Distributed Denial of Service (DDoS) attacks are still challenging for current datacenter and Internet packet exchange operators. Detecting volumetric attacks are in the range of seconds, whereas their mitigation is often in the range of minutes. Besides the fact that the attacks are effective until their mitigation is successful, there are further attacks that remain unnoticed by current equipment. These are hit-and-run attacks that last for a fraction of a second or a few seconds only, pushing the network or the targeted service towards an unstable state and evaporate. This paper presents an FPGA-based DDoS detector and its application. The detector is capable of detecting the top-9 DDoS attack types, the 96.67% of all DDoS attacks, and the so called hit-and-run attacks within milliseconds. The concept is validated through real-life use cases on attacks of a medium-sized datacenter network.

While the scale, frequency and impact of the recent cyber- and DoS-attacks have all increased, the traditional security management systems are still supervised by human operators in the decisional loop. To cope with the new breed of machine-driven attacks — particularly those designed to overload the humans in the loop — the next-generation anomaly detection and attack mitigation schema, i.e. the network security management, must improve greatly in speed and accuracy: become machine-driven, too. As infrastructure we propose an FPGA-accelerated Network Function Virtualization that potentially enhances the current multi-Tbps switching fabrics with SDN-based security capabilities of vastly higher performance and scalability. As key novelties, we contribute (i) sub-ms detection lag (ii) of the top 9 Akamai attacks [1] with (iii) a real-time SDN feedback loop between a distributed programmable data plane and a centralized SDN controller, (iv) coupled via a global N:1 mirror. We validate the concept in an actual datacenter network with a new security application that can detect and mitigate real-world dDoS attacks, with lags from 430 us up to 3 ms — several orders of magnitude faster than before.

AIM To assess the prevalence of a panel of serologic markers that reflect gut barrier dysfunction in a mixed cohort of pediatric and adult primary sclerosing cholangitis (PSC) patients. METHODS Sera of 67 PSC patients [median age (range): 32 (5-79) years, concomitant IBD: 67% and cirrhosis: 20%] were assayed for the presence of antibodies against to F-actin (AAA IgA/IgG) and gliadin (AGA IgA/IgG)] and for serum level of intestinal fatty acid-binding protein (I-FABP) by ELISA. Markers of lipopolysaccharide (LPS) exposure [LPS binding protein (LBP)] and various anti-microbial antibodies [anti-OMP Plus IgA and endotoxin core IgA antibody (EndoCAb)] were also determined. Poor disease outcome was defined as orthotopic liver transplantation and/or liver-related death during the follow-up [median: 99 (14-106) mo]. One hundred and fifty-three healthy subjects (HCONT) and 172 ulcerative colitis (UC) patients were the controls. RESULTS A total of 28.4%, 28.0%, 9% and 20.9% of PSC patients were positive for AAA IgA, AAA IgG, AGA IgA and AGA IgG, respectively. Frequencies of AAA IgA and AAA IgG (P < 0.001, for both) and AGA IgG (P = 0.01, for both) but not AGA IgA were significantly higher compared to both of the HCONT and the UC groups. In survival analysis, AAA IgA-positivity was revealed as an independent predictor of poor disease outcome after adjusting either for the presence of cirrhosis [HR = 5.15 (1.27-20.86), P = 0.022 or for the Mayo risk score (HR = 4.24 (0.99-18.21), P = 0.052]. AAA IgA-positivity was significantly associated with higher frequency of anti-microbial antibodies (P < 0.001 for EndoCab IgA and P = 0.012 for anti-OMP Plus IgA) and higher level of the enterocyte damage marker (median I-FABPAAA IgA pos vs neg: 365 vs 166 pg/mL, P = 0.011), but not with serum LBP level. CONCLUSION Presence of IgA type AAA identified PSC patients with progressive disease. Moreover, it is associated with enhanced mucosal immune response to various microbial antigens and enterocyte damage further highlighting the importance of the gut-liver interaction in PSC.

Mannose-binding lectin (MBL) is a serum lectin synthesized by the liver and involved in innate host defense. MBL deficiency increases the risk of various infectious diseases mostly in immune-deficient conditions. Bacterial infections are a significant cause of morbidity and mortality in liver cirrhosis due to the relative immuncompromised state.Sera of 929 patients with various chronic liver diseases [autoimmune liver diseases (ALD), 406; viral hepatitis C (HCV), 185; and liver cirrhosis (LC) with various etiologies, 338] and 296 healthy controls (HC) were assayed for MBL concentration. Furthermore, a follow-up, observational study was conducted to assess MBL level as a risk factor for clinically significant bacterial infections in cirrhotic patients.MBL level and the prevalence of absolute MBL deficiency (100 ng/ml) was not significantly different between patients and controls (ALD: 14.5%, HCV: 11.9%, LC: 10.7%, HC: 15.6%). In cirrhotic patients, the risk for infection was significantly higher among MBL deficient subjects as compared to non-deficient ones (50.0% vs. 31.8%, p=0.039). In a logistic regression analysis, MBL deficiency was an independent risk factor for infections (OR: 2.14 95% CI: 1.03-4.45, p=0.04) after adjusting for Child-Pugh score, co-morbidities, gender, and age. In a Kaplan-Meier analysis, MBL deficiency was associated with a shorter time to develop the first infectious complication (median days: 579 vs. 944, pBreslow=0.016, pLogRank=0.027) and was identified as an independent predictor in a multivariate Cox-regression analysis (p=0.003, OR: 2.33, 95% CI: 1.34-4.03).MBL deficiency is associated with a higher probability and shorter time of developing infections in liver cirrhosis, further supporting the impact of the MBL molecule on the host defense.

A gastrooesophagealis refluxbetegség (GERD) kialakulásában az alsó nyelőcsősphincter (LES) elernyedése és a csökkent LES-tónus mellett a fokozott hasűri nyomás is szerepet játszhat. Célkitűzés: Annak vizsgálata, hogy az éveken át tartó, foglalkozással járó fokozott hasűri nyomás, hasprés, erőlködés növeli-e a GERD kialakulásának kockázatát. Módszer: A refluxtüneteket kérdőív segítségével kontrollcsoporthoz viszonyítva hivatásos énekesek, fúvós hangszeren játszó művészek és üvegfúvók között értékelték. Eredmények: A hivatásos énekesek között a gyomorégés, a regurgitatio és a rekedtség a lényegességi szintet meghaladóan gyakrabban fordult elő ( p p p p p Következtetések: Eredményeik arra utalnak, hogy azon foglalkozások esetén, ahol tartósan fokozott a hasűri nyomás, a refluxtünetek gyakrabban fordulnak elő. Ilyen szempontból a GERD foglalkozási ártalomnak is tekinthető.

Before the advent of FPGAs (Field Programmable Gate Arrays), hardware acceleration of networking equipment has been implemented through static architectural elements. The new generations of these highly flexible FPGA architectures can be reconfigured on-the-fly, allow parallell processing of data arriving at high-speed, and even contain hundreds of DSPs (Digital Signal Processors), to further parallelize certain, computationally intensive tasks. This paper demonstrates some of the capabilities of a new, FPGA-based networking platform, C-GEP. This multi-purpose, programmable platform can support various tasks, from being a high-speed switch/router, through pre-processing packets for Deep Packet Inspection, towards being the Forwarding Plane element in the SDN infrastructure. The current demonstration contains two further implementations of 100 Gbit/s-capable applications: a traffic generator — firing off multi-encapsulated packets — and a lossless traffic monitor — that is able to classify and steer the monitored traffic to further post-processors.

Programmable networking platforms are in the spotlight since the advent of SDN (Software Defined Networking). It is a great challenge to create such a platform — especially with reconfigurable hardware and line-rate capabilities reaching and exceeding 100 Gbit/s. These requirements together put FPGA (Field Programmable Gate Array) technology into the focus of high performance networking. In this paper, we introduce a highly flexible, programmable, multi-purpose networking platform, which is capable of hosting multiple 1 and 10 Gbit/s Ethernet interfaces — beside their 40 or 100 Gbit/s interface. The hardware of the introduced C-GEP platform is reconfigurable, even on-the-fly; due to the FPGA technology. C-GEP can host a wide range of high-speed network specific applications — including monitoring, switching and media conversion —, and it is aligned with the SDN principles. The system consists of two main building blocks: a high performance FPGA-based custom specific hardware platform and the firmware tailored to the actual task. The architecture is briefly introduced by its hardware and firmware setup, then some of the core functionalities, such as packet processing, filtering, and switching are presented.

As the line rate reaches and exceeds 100 Gbit/s, the usage of hardware-accelerated networking equipment is getting a natural choice when evaluating newly developed network-related features. The requirement for high throughput and high level of reconfiguration together put Field Programmable Gate Array (FPGA) technology into the focus of high performance networking. In this demonstration, we show some of the capabilities of a new, 100 Gigabit Ethernet Evaluation Platform, called C-GEP. Since the hardware is reconfigurable, the platform can host a wide range of high-speed network specific applications, and it is aligned with the Software Defined Networking (SDN) principles. Our demonstration contains two different implementations of 100 Gbit/s-capable applications: a traffic generator and a traffic monitor engine. Our aim here is to show the feasibility of C-GEP for high-speed networking evaluations.

Carrying out network monitoring tasks remains a continuous challenge, partially because the line rate reaches and exceeds 100 Gbit/s. Besides the increasing data rate, the advent of programmable networks necessitates efficient solutions for supporting packet processing tasks in an adaptive way. Introducing a modification of a protocol or any new protocol in such a flexible infrastructure implies a novel management approach incorporating network monitoring equipment with reconfigurable architecture. The requirement for high throughput and high level of reconfiguration together put Field Programmable Gate Array (FPGA) technology into the focus of high performance networking. In this paper, we introduce a programmable, multi-purpose network platform called C-GEP that is based on a reconfigurable architecture. The system consists of two main building blocks: a high performance FPGA-based custom hardware platform and a firmware dedicated for network monitoring. We present the architecture focusing on the system-level integration of specific packet processors. The integration of processing building blocks into one high performance system has great challenges. These are primarily related to specific, limiting factors of system resources — which we discuss also in this paper.

This paper describes a unique path of estimating the Quality of Experience (QoE) for streaming video. Instead of following the widely researched idea of correlating video degradation with Quality of Service (QoS) metrics of the network, we propose to merely analyze the nature of packet losses. The majority of today's streaming video traffic is using compressed formats, where the videos are composed from a series of key, predicted, and bi-predictive frames (I frame, P frame, B frame, respectively). The content of these frames gets packetized, and sent over the network as video traffic. Losing packets that belong to I, P and B frames lead to QoE degradations of different severity. The degrading effect of these packet losses depend on the type of the video (two extremes can be slowly moving balloons versus fireworks in the sky), the type of frame, the volume of the lost packets, and further factors. The aim of this paper is to introduce a measurement and analysis method for correlating packet loss patterns of key, predicted and bi-predictive frames with objective quality metrics, such as the SSIM (Structural SIMilarity index). Furthermore, measurement results on the effect of such packet losses for various video types are also presented in this paper.

Network packet parsing and packet forwarding are general tasks for all routing devices. However, the requirement for line-rate packet processing, independently from the transmission technology, is a common demand against core network equipments. In this paper, we investigate programmable hardware architectures (i.e., Field Programmable Gate Array FPGA) as central building blocks of the data plane for state-of-the-art 100 Gbit/s network devices. We reveal the benefits and drawbacks of the available hardware architectures (such as Network Processors, Application-Specific Integrated Circuits (ASIC) and FPGAs, respectively). After showing the general packet processing steps on programmable hardware, we describe the problem space of line-rate packet processing in relation to the evolution of transmission technologies, i.e., 1, 10, 100 Gbit/s Ethernet and beyond. Moreover, we present design trade-offs, such as operational frequency, data path width and resource requirement, covering the 1 to 400 Gbit/s throughput range and we propose best practices for their hardware designs.

In this work, we are about to introduce a high performance NetFPGA based network measurement system, called Rnetprobe that implements a dual, multi-layer timestamping method for QoS analysis. The multi-layer timestamping idea came from the demand to perform end-to-end active measurements that enable improved cross-layer analysis to evaluate QoS for time sensitive services. Accordingly, for each captured packet one timestamp is generated at MAC level, which is provided by our FPGA hardware module, while another timestamp is tagged to the packet on its processing path as soon as it becomes available to the OS kernel's network stack. This second timestamp is software based and therefore reflects to the packet processing characteristics of the OS kernel. In this paper, we are introducing the mentioned multi-layer timestamping method and are evaluating its performance.

The main aim of the present paper is to draw the attention of the readers of this special issue to the modeling issues of sensor networks. The novelty of this investigation is the introduction of servers vacation combined with priority customers for finite-source retrial queues and its application to wireless sensor networks. In this paper we analyze a priority finite-source retrial queue with repeated vacations. Two types of priority customers are defined, customers with priority 1 (P1) go directly to an ordinary FIFO queue. However, if customers with priority 2 (P2) find the server in busy or unavailable state go to the orbit. These customers stay in the orbit and retry their request until find the server in idle and available state. We assume that P1 customers have non-preemptive priority over P2 customers. The server starts with a listening period and if no customer arrive during this period it will enter in the vacation mode. When the vacation period is terminated, then the node wakes up. If there is a P1 customer in the queue the server begin to serve it, and when there is no any P1 customer, the node will remain awake for exponentially distributed time period. If that period expires without arrivals the node will enter in the next sleeping period. All random variables involved in model construction are supposed to be independent and exponentially distributed ones. Our main interest is to give the main steady-state performance measures of the system computed by the help of the MOSEL tool. Several Figures illustrate the effect of input parameters on the mean response time.

Generic purpose multi-core PC architectures are facing performance challenges of high rate packet reception on gigabit per second and higher speed network interfaces. In order to assign a CPU core to a networking softIRQ, the single input queue design of the low-level packet processing subsystem relies on the kernel's Symmetric Multiprocessing (SMP) scheduler, which does not perform load balancing of the softIRQ instances between the CPU cores. In practice, when single receive queue is used all of the softIRQs are assigned to a single CPU core. This typical arrangement could easily drive to CPU resource exhaustion and high packet loss ratio on high bandwidth interfaces. The non-steady state of the system is triggered by the high arrival rate of the packets. This work presents a proposal for improving the packet processing efficiency in single input queue multi-core systems.

Widely used network measurement applications, such as tcpdump and Wireshark, use the same common libpcap packet capture library. Libpcap assigns a 10-6 second precision timestamp to all processed frames. Higher physical bandwidth implies shorter inter-arrival times between consecutive frames. Therefore timestamp precision must be proportional to the link speed. Latest version 1.0.x of libpcap provides 10-6 second native resolution, however pcap format supports a larger 2 x 32-bit timestamp value for each stored packets. On Gigabit Ethernet or faster networks, timestamp resolution that works in the microsecond domain may not enable us to precisely reproduce the time-domain relation between consecutive frames. Therefore overall analysis of the data transmission could drive to a false result. Independently from one other, five impact factors could directly bias the generation of timestamps: hardware architecture, NIC driver operation mode, clock source, kernel queue handler and the libpcap itself. In an idealized case generated timestamps are always converging and suitably close to the real arrival or transmission time of each frames so to conserve the original inter-arrival time values. For packet capturing with libpcap, it is assumed that timestamping performed when a frame is enqueued to the kernel’s input packet queue. Accordingly these timestamps represents the time moment when a frame reaches the input queue. Libpcap must retrieve these timestamps from the kernel. Timestamp resolution of network measurement applications must be increased according to the requirements of advanced high speed data networks. In our paper we are going to show an alternative libpcap-based solution that features nanosecond precision timestamping.

BACKGROUND: Bacterial translocation plays important role in the complications of liver cirrhosis. Antibody formation against various microbial antigens is common in Crohn's disease and considered to be caused by sustained exposure to gut microflora constituents. We hypothesized that anti-microbial antibodies are present in patients with liver cirrhosis and may be associated with the development of bacterial infections. METHODOLOGY/PRINCIPAL FINDINGS: Sera of 676 patients with various chronic liver diseases (autoimmune diseases: 266, viral hepatitis C: 124, and liver cirrhosis of different etiology: 286) and 100 controls were assayed for antibodies to Saccharomyces cerevisiae (ASCA) and to antigens derived from two intestinal bacterial isolates (one gram positive, one gram negative, neither is Escherichia coli). In patients with liver cirrhosis, we also prospectively recorded the development of severe episodes of bacterial infection. ASCA and anti-OMP Plus™ antibodies were present in 38.5% and 62.6% of patients with cirrhosis and in 16% and 20% of controls, respectively (p

DNA fragmentation. Total RNA was isolated and IL-8, CXCL1, CXCL2, CCL2, ICAM, VCAM mRNA expression was determined by real time RT-PCR. NF-kB activation was determined by luciferase assay. Results: Exposure of LX2 cells to palmitate significantly induces IL-8 production and gene expression, as well as TLR4, CXCL1, CXCL2, CCL2, ICAM, VCAM mRNA expression. Palmitate induced IL-8 production can not be blocked by pan-caspase inhibitor. However, palmitate induced MIP-2 (rodent homolog of human IL-8) production was completely abrogated in HSCs from TLR4-mutant (C3H/HeJ) mice, but not from wildtype (C3H/HeOuJ) mice. Palmitate also induces NF-kB activation in a dose-dependent manner. Conclusions: Our data demonstrate that palmitate directly stimulates IL-8 production in HSCs via TLR4 signaling pathway, suggesting that HSCs play an important role in FFAs induced liver inflammation and injury.