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This study addresses the complementary metal-oxide-semiconductor-compatible fabrication of vertically stacked Si/SiO2/Si nanopillars (NPs) with embedded Si nanodots (NDs) as key functional elements of a quantum-dot-based, gate-all-around single-electron transistor (SET) operating at room temperature. The main geometrical parameters of the NPs and NDs were deduced from SET device simulations using the nextnano++ program package. The basic concept for single silicon ND formation within a confined oxide volume was deduced from Monte-Carlo simulations of ion-beam mixing and SiOx phase separation. A process flow was developed and experimentally implemented by combining bottom-up (Si ND self-assembly) and top-down (ion-beam mixing, electron-beam lithography, reactive ion etching) technologies, fully satisfying process requirements of future 3D device architectures. The theoretically predicted self-assembly of a single Si ND via phase separation within a confined SiOx disc of < 500 nm³ volume was experimentally validated. This work describes in detail the optimization of conditions required for NP/ND formation, such as the oxide thickness, energy and fluence of ion-beam mixing, thermal budget for phase separation and parameters of reactive ion beam etching. Low-temperature plasma oxidation was used to further reduce NP diameter and for gate oxide fabrication whilst preserving the pre-existing NDs. The influence of critical dimension variability on the SET functionality and options to reduce such deviations are discussed. We finally demonstrate the reliable formation of Si quantum dots with diameters of less than 3 nm in the oxide layer of a stacked Si/SiO2/Si NP of 10 nm diameter, with tunnelling distances of about 1 nm between the Si ND and the neighboured Si regions forming drain and source of the SET.

This study analyzes the CMOS compatibility in the manufacturing of a hybrid SET-FET circuit. The fundamental element towards an operating SET at room temperature is a vertical nanopillar with embedded Si nanodot generated by ion-beam irradiation. The integration process from nanopillars to contacted SETs is validated by structural characterization. Then, the monolithic fabrication of planar FETs co-integrated with vertical SETs is presented, and its compatibility with standard CMOS technology is demonstrated. The work includes process optimization, pillar integrity validation, electrical characterization and simulation taking into account parasitic elements. The FET fabrication process is adapted to meet the requirements of the pre-fabricated nanopillars. Overall, this work establishes the groundwork for the realization of a hybrid SET-FET circuit operating at room temperature.

The inherent three-dimensional topology of vNWs imposes several constraints to their fabrication and their integration in other circuits. We present here the use of Hydrogen silsesquioxane (HSQ) for the fabrication of single electron transistors (SETs) based on vNWs.

This work reports the CMOS compatible and monolithic fabrication of a conventional planar field effect transistor (FET) co-integrated with a quantum dot (QD) based single electron transistor (SET). The FET process fabrication is adapted to fulfill the restrictions imposed by the pre-fabricated SET, such as reduced thermal budget, extra protection layers and modified doping in order to obtain low threshold voltage. The resulting FET presents good subthreshold characteristics and the SET preserves its integrity at the end of the fabrication.

This article is part of the Thematic Series "Advanced atomic force microscopy"., Micro and Nano Engineering