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This paper describes and addresses the challenges that are encountered while designing a 900 GHz antenna for FET detectors using a standard submicron CMOS technology. The reduced metal stack, the problem of surface waves and technology-related rules are taken into account in order to properly design an efficient antenna, with the objective to couple it to field-effect transistor (FET) detectors in a focal-plane array configuration. Simulations on a 0.15-μm standard CMOS technology show that up to 58% efficiency with responsivity in the several kV/W range can be achieved.

SPADnet is a sensor platform for the detection and processing of gamma photons generated in a PET system. SPADnet uses the novel technique of deferred coincidence detection, whereas timestamps associated with gamma events and their energy are routed at high speed (up to 3.3 million events per second) over a 2Gbps network, along with synchronization information. In this work, we describe SPADnet's key building block, a tile of SPADnet-I chips. SPADnet-I is a 50 mm2, 8x16 pixel digital SiPM where each pixel includes an array of 720 SPADs and the logic to count photons and record their arrival time. A fill factor of 42.9% is achieved. A distributed adder provides the number of photons detected throughout the whole array every 10 ns. On-chip triggering logic monitors this value in real time to discriminate gamma events from dark counts. The chip features a 10.8% energy resolution and a CRT of 288ps when coupled to a 3x3x10 mm3 LYSO crystal. High spatial resolution is obtained by combining the data generated by each pixel to efficiently locate the gamma absorption in the 2D space even when coupled to large arrays of crystal needles as small as 1.12x1.12mm2. The tile is built on a 5x5 array of SPADnet-I sensors. A Xilinx Spartan6 FPGA controls the whole module and monitors the gamma activity across the 25 sensors. Here, the large amount of data generated for each detected gamma is processed in real time to extract energy, position and time-of-arrival. Pile-up detection and energy windowing are applied to the events, which are then fed to a network of tiles for coincidence detection. A centralized snooper recognizes coincidence pairs while thermal, Compton, and single events are discarded. The system is inherently scalable, as it enables single- or multi-rings of photonic modules for potentially large PET systems.

n this paper we illustrate the core technologies at the basis of the European SPADnet project (www.spadnet.eu), and present the corresponding first results. SPADnet is aimed at a new generation of MRI-compatible, scalable large area image sensors, based on CMOS technology, that are networked to perform gamma-ray detection and coincidence to be used primarily in (Time-of-Flight) Positron Emission Tomography (PET). The project innovates in several areas of PET systems, from optical coupling to single-photon sensor architectures, from intelligent ring networks to reconstruction algorithms. In addition, SPADnet introduced the first computational model enabling study of the full chain from gamma photons to network coincidence detection through scintillation events, optical coupling, etc.

This work introduces a design procedure for two-stage class AB opamps which minimizes power consumption for a given specifications set. The proposed procedure has been applied to the redesign of published opamps for comparison target, demonstrating the procedure validity by improving their efficiency. The systematic procedure is then applied to an opamp that will be part of the readout of an imager. The opamp is designed in a 0.35 /spl mu/m 3.3V standard CMOS technology and exhibits GBW /spl equiv/49MHz, SR /spl equiv/ 74V//spl mu/s, 0.1% settling time of 43ns, consuming only 0.87mW with a die area of 0.0053mm/sup 2/.

A complete front-end system for resistive gas sensor array is presented. The system is composed by a substrate temperature control circuit and by a read-out circuit. The temperature control allows maintaining a 100/spl deg/C temperature gradient selected in the temperature range [150/spl deg/C-350/spl deg/C] on the array of sensor. The gas sensor read-out circuit, which acts like a resistance-to-period converter, is suitable to be interfaced to a microcontroller in order to achieve a resolution error lower than 0.5% for a resistance ranging in (300k/spl Omega/-300M/spl Omega/]. The full device, including 8 read-out channels and 2 temperature control systems, is designed in a standard 0.35/spl mu/m CMOS technology. The die area is 1.8mm/sup 2/ with a total power consumption of 30mW from a single 3.3V supply voltage.