410 results on '"Per Stenström"'
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2. DNNOPT: A Framework for Efficiently Selecting On-chip Memory Loop Optimizations of DNN Accelerators.
3. SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations.
4. SCALE: Secure and Scalable Cache Partitioning.
5. eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem.
6. Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints.
7. GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases.
8. Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications.
9. Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints.
10. Bounding the execution time of parallel applications on unrelated multiprocessors.
11. CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling.
12. DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors.
13. Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints.
14. A GPU Register File using Static Data Compression.
15. Federated Scheduling of Sporadic DAGs on Unrelated Multiprocessors.
16. SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations.
17. QoS-Driven Coordinated Management of Resources to Save Energy in Multi-core Systems.
18. SaC: Exploiting Execution-Time Slack to Save Energy in Heterogeneous Multicore Systems.
19. Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems.
20. ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness.
21. Rock: a framework for pruning the design space of hybrid main memory systems.
22. Timing-Anomaly Free Dynamic Scheduling of Task-Based Parallel Applications.
23. Global Dead-Block Management for Task-Parallel Programs.
24. Scheduling Parallel Real-Time Recurrent Tasks on Multicore Platforms.
25. Trends on heterogeneous and innovative hardware and software systems.
26. Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories.
27. RADAR: Runtime-assisted dead region management for last-level caches.
28. EUROSERVER: Share-anything scale-out micro-server design.
29. Runtime-Assisted Global Cache Management for Task-Based Parallel Programs.
30. A Framework for Automated and Controlled Floating-Point Accuracy Reduction in Graphics Applications on GPUs.
31. SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures.
32. Performance Impact of Batching Web-Application Requests Using Hot-Spot Processing on GPUs.
33. HyComp: a hybrid cache compression method for selection of data-type-specific compression methods.
34. Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers.
35. Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints.
36. Coordinated Management of DVFS and Cache Partitioning under QoS Constraints to Save Energy in Multi-Core Systems.
37. PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor.
38. Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures.
39. Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell.
40. SC2: A statistical compression cache scheme.
41. Crystal: A Design-Time Resource Partitioning Method for Hybrid Main Memory.
42. Overhead-aware temporal partitioning on multicore processors.
43. Efficient Forwarding of Producer-Consumer Data in Task-Based Programs.
44. Improving data access efficiency by using a tagless access buffer (TAB).
45. HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory.
46. Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints
47. Transactional prefetching: narrowing the window of contention in hardware transactional memory.
48. π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.
49. The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.
50. Classification and Elimination of Conflicts in Hardware Transactional Memory Systems.
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