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With the advancement of integrated circuit technology, nanoscale latches operating in space environments are more sensitive to single-event multiple-node upset. Based on the polarity design, this article proposes an N-polarity cell (N-cell) and a P-polarity cell (P-cell), which can block the propagation of double-node upset (DNU). Then, a low-overhead DNU self-recoverable latch (LODRL) is proposed, which consists of a DNU self-recoverable (DNUR) core structure and a clock-gated inverter. Compared with state-of-the-art DNUR latches, the proposed LODRL has an average reduction of 17.07%, 52.62%, 31.23%, and 78.81% in area, power consumption, delay, and power–delay–area product (PDAP), respectively. Furthermore, a high-performance DNU self-recoverable and triple-node-upset tolerant latch (DRTTL) is proposed, which consists of a DNUR core, a clock-gated inverter, and an interlocked structure. Compared with these advanced triple-node-upset (TNU)-tolerant latches, the DRTTL has an average reduction of 17.7%, 41.91% and 56.25% in power consumption, delay, and PDAP, respectively. The DRTTL is also insensitive to a high-impedance state and process, voltage, and temperature variations, exhibits a large critical charge, and can achieve complete DNU self-recovery and 90% TNU self-recovery. Therefore, the DRTTL features low overhead and high performance, which is suitable for applications in aerospace environments.

The impact of process variations on the read operation of low-voltage STT-MRAM becomes severe, posing a challenge in determining the optimal sensing timing of the sense amplifier. This study investigates techniques for refining the timing scheme of sensing circuits in order to improve the sensing reliability of the STT-MRAM. The supply voltage $V_{DD}$ , the Tunneling Magnetoresistance Ratio TMR, the low resistance state of bit-cell $R_{P}$ , and the parasitic capacitance of bit-line $C_{BL}$ are analyzed along with the voltage sense amplifier (VSA) involved in sensing yield. We develop a timing model through theoretical analysis to determine the optimal VSA enable signal (SAE). In addition, an innovative Process-Voltage-Temperature (PVT) tracking scheme is proposed that can track the optimal VSA enable signal (SAE) and suppress timing variations. Monte-Carol simulation in the 28nm CMOS and magnetic tunnel junction (MTJ) process confirms that the combined scheme significantly enhances the robustness of sensing operation. The proposed scheme improves yield by 20% to 35%, reduces power consumption by 43% to 63%, and reduces read access delay by 47% to 59% compared to conventional sensing schemes at 0.6V supply voltage.

As the physical size of dynamic random-access memory (DRAM) technology continues to decrease, the effects of process fluctuations on the transistor-threshold voltage are becoming increasingly serious. The offset voltage as a key parameter of the core circuit, is caused by the mismatch of the transistor threshold voltage in the sense-amplifier (SA) and it significantly affects the accuracy of data read from DRAM. Therefore, this brief analyzes the timings, working processes, and simulations of three SA circuits, the offset cancellation sense amplifier (OCSA), boosted reference voltage sense amplifier (BRVSA), and offset mismatch calibration sense amplifier (OMCSA). Subsequently, a novel flip point offset-compensation sense amplifier (FPOCSA) is proposed. An offset voltage storage cell is formed during the self-calibration phase owing to the offset-compensation effect of the flip point. Moreover, the bit-line voltage difference is amplified to improve the sensing margin and robustness. According to the post-layout simulation results under 65nm CMOS technology, the standard deviation of the FPOCSA offset voltage is 3.50 mV, which is 70.6%, 47.6%, and 21.2% lower than OCSA, BRVSA, and OMCSA, respectively.

A soft-error-immune quadruple-node-upset tolerant latch (SEI-QNUTL) with a low delay and high performance is proposed using 65-nm CMOS technology. The proposed SEI-QNUTL design consists of three soft-error-immune static random access memory (SEI-SRAM) cells. Furthermore, each SEI-SRAM cell employs polarity design and source-isolation technology to reduce the number of sensitive nodes and enhance the reliability of the latch. Compared with state-of-the-art quadruple-node-upset (QNU) tolerant latches [including high-performance and low-cost single-event multiple-node-upsets resilient (HLMR), QNU tolerant latch (QNUTL), and Latch Design and Algorithm-based Verification Protected against Multiple-Node-Upsets (LDAVPM)], the proposed SEI-QNUTL design reduces (on average) the area, delay, and area-power-delay-product (APDP) by 47.0%, 25.0%, 46.5%, and 66.3%, respectively. Extensive variation analysis validates that the SEI-QNUTL design is less sensitive to process, voltage, and temperature (PVT) variations regarding power consumption and delay. Furthermore, Monte Carlo (MC) simulations show that the proposed latch exhibits high reliability when performing data storage. Compared with the existing latches, the SEI-QNUTL design makes a good tradeoff among delay, power, and area, and it can thus be used in safety-critical applications.

The application of non-volatile memory technology is increasingly attractive for Computing-in-memory (CIM) owing to high integration density and negligible standby power consumption. This study proposes an spin-transfer-torque (STT) magnetic random access memory (MRAM) based CIM macro which incorporates following innovative features: 1) cross-feedback margin-boost (CFMB) scheme to enable robust and fast reading operations against process variation and limited Tunneling Magnetoresistance Ratio (TMR); 2) cascade computing units (CCU) and related design method for efficient and stable multi-bit multiply-and-accumulate (MAC) operation; and 3) dual computing mode scheme and resolution adjustable quantization module to optimize energy efficiency and operating speed. The post-simulations are performed under 28nm CMOS&MTJ technology. The results demonstrate the achievement in energy efficiency of 36.4 TOPS/W while performing MAC operations with up to 16-bit weights, 4-bit inputs, and 22-bit outputs.