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Simple innate behavior is often described as hard-wired and largely inflexible. Here, we show that the avoidance of hot temperature, a simple innate behavior, contains unexpected plasticity in Drosophila. First, we demonstrate that hot receptor neurons of the antenna and their molecular heat sensor, Gr28B.d, are essential for flies to produce escape turns away from heat. High-resolution fly tracking combined with a 3D simulation of the thermal environment shows that, in steep thermal gradients, the direction of escape turns is determined by minute temperature differences between the antennae (0.1°–1 °C). In parallel, live calcium imaging confirms that such small stimuli reliably activate both peripheral thermosensory neurons and central circuits. Next, based on our measurements, we evolve a fly/vehicle model with two symmetrical sensors and motors (a “Braitenberg vehicle”) which closely approximates basic fly thermotaxis. Critical differences between real flies and the hard-wired vehicle reveal that fly heat avoidance involves decision-making, relies on rapid learning, and is robust to new conditions, features generally associated with more complex behavior., Simões, Levy et al. use a combination of experiments and models to study how Drosophila flies steer away from dangerous heat. They discover that flies use small temperature differences between the antennae to turn clear of thermal danger; they also demonstrate that heat avoidance, a simple innate behavior, contains unexpected plasticity.

The standard and layout-hardened D filp-flops (DFFs) named DFF1–6 were designed and manufactured based on an advanced 22-nm ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) technology. Heavy-ion irradiation results indicate that FD-SOI technology has contributions to radiation hardness and the hardened DFFs have higher single-event upset (SEU) tolerance than the standard DFF. The upsets induced by the embedded SET targets are strongly dependent on the testing frequency. The layout separating the dual interlocked storage cell (DICE) structure can prevent the direct occurrence of SEU in flip-flop cells, and upsets were removed completely in two-fold DICE structure DFFs.

Reliability of ferroelectric random access memories (FRAMs) is an important issue in Space application. In this work, we investigated the impact of total ionizing dose (TID) on single event effect (SEE) sensitivity of FRAMs. Five types of errors were detected. The event cross section detected in dynamic tests decreased after irradiation. Biased devices during TID irradiation had a greater decrease in event cross section than unbiased devices. TCAD simulations were performed to investigate the effects of heavy ions on memory cells of FRAMs. The collected charges at the drain of NMOS transistors induced by incident ions had a negative impact on polarized state of the ferroelectric capacitors.

The total ionizing dose (TID) effects on single-event upset (SEU) hardness are investigated for two silicon-on-insulator (SOI) static random access memories (SRAMs) with different layout structures in this paper. The contrary changing trends of TID on SEU sensitivity for 6T and 7T SOI SRAMs are observed in our experiment. After 800 krad(Si) irradiation, the SEU cross-sections of 6T SRAMs increases by 15%, while 7T SRAMs decreases by 60%. Experimental results show that the SEU cross-sections are not only affected by TID irradiation, but also strongly correlate with the layout structure of the memory cells. Theoretical analysis shows that the decrease of SEU cross-section of 7T SRAM is caused by a raised OFF-state equivalent resistance of the delay transistor N5 after TID exposure, which is because the radiation-induced charges are trapped in the shallow trench, and isolation oxide (STI) and buried oxide (BOX) enhance the carrier scattering rate of delay transistor N5.

The interaction of radiation with three-dimensional (3D) electronic devices can be determined through the detection of single-event effects (SEU). In this study, we propose a method for the evaluation of SEUs in 3D static random-access memories (SRAMs) induced by heavy-ion irradiation. The cross-sections (CSs) of different tiers, as a function of the linear energy transfer (LET) under high, medium, and low energy heavy-ion irradiation, were obtained through Monte Carlo simulations. The simulation results revealed that the maximum value of the CS was obtained under the medium-energy heavy-ion penetration, and the effect of penetration range of heavy ions was observed in different tiers of 3D-stacked devices. The underlying physical mechanisms of charge collection under different heavy-ion energies were discussed. Thereafter, we proposed an equation of the critical heavy-ion range that can be used to obtain the worst CS curve was proposed. Considering both the LET spectra and flux of galactic cosmic ray (GCR) and the variation in the heavy-ion Bragg peak values with the atomic number, we proposed a heavy-ion irradiation test guidance for 3D-stacked devices. In addition, the effectiveness of this method was verified through simulations of the three-tier vertically stacked SRAM and the ultrahigh-energy heavy-ion irradiation experiment of the two-tier vertically stacked SRAM. this study provides a theoretical framework for the detection of SEUs induced by heavy-ion irradiation in 3D-integrated devices.

Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

DICE hardened configuration logics in million-gate FPGA were investigated. The rectangular parallelepiped models were established based on the material details and the layout of FPGA. Multiple sensitive volumes and charge collection weights were ascertained. The simulations were matched and further explained our heavy ion experiments.

Single event effects of 1-T structure programmable read-only memory (PROM) devices fabricated with a 130-nm complementary metal oxide semiconductor-based thin/thick gate oxide anti-fuse process were investigated using heavy ions and a picosecond pulsed laser. The cross sections of a single event upset (SEU) for radiation-hardened PROMs were measured using a linear energy transfer (LET) ranging from 9.2 to 95.6 MeV cm2 mg−1. The result indicated that the LET threshold for a dynamic bit upset was ~ 9 MeV cm2 mg−1, which was lower than the threshold of ~ 20 MeV cm2 mg−1 for an address counter upset owing to the additional triple modular redundancy structure present in the latch. In addition, a slight hard error was observed in the anti-fuse structure when employing 209Bi ions with extremely high LET values (~ 91.6 MeV cm2 mg−1) and large ion fluence (~ 1 × 108 ions cm−2). To identify the detailed sensitive position of a SEU in PROMs, a pulsed laser with a 5-μm beam spot was used to scan the entire surface of the device. This revealed that the upset occurred in the peripheral circuits of the internal power source and I/O pairs rather than in the internal latches and buffers. This was subsequently confirmed by a 181Ta experiment. Based on the experimental data and a rectangular parallelepiped model of the sensitive volume, the space error rates for the used PROMs were calculated using the CREME-96 prediction tool. The results showed that this type of PROM was suitable for specific space applications, even in the geosynchronous orbit.

The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-flops. This radiation hardened circuits include large-spacing interlock CRAM cells, area saving debugging logics, the redundant flip-flops cells, and error mitigated 6-T EBRAMs. Heavy ion irradiation test result indicates that the hardened CRAMs had a high linear energy transfer threshold of upset &sim, 18 MeV/(mg/cm 2 ) with an extremely low saturation cross-section of 6.5 &times, 10 &minus, 13 cm 2 /bit, and 71% of the upsets were single-bit upsets. The combinational use of triple modular redundancy and check code could decline &sim, 86.5% upset errors. Creme tools were used to predict the CRAM upset rate, which was merely 8.46 &times, 15 /bit/day for the worst radiation environment. The effectiveness of radiation tolerance has been verified by the irradiation and prediction results.

Numerical simulation of single event effect in 3D stacked NMOS transistor, inverter and 6T SRAM cell models were conducted using Geant4 and TCAD combined technology. Heavy ion track straggling effect was observed in 3D stacked transistor and inverter models by comparing the ion induced transient pulses and ion striking positions. TRIM simulation was carried out to study and verify the ion track straggling effect in 3D stacked models, which is much more significant for low energy heavy ions than high energy counterparts. Large scale simulation of upset sensitive area imaging in stacked 6T SRAM cell model showed that the upset areas (or cross sections) in each tier are very similar. It indicated that high energy heavy ions are beneficial to the SEE analysis of 3D stacked devices and almost can remove the ion track straggling effect, but which is only appropriate for the relatively thin devices. Finally, the problems on SEE evaluation and analysis in future 3D stacked devices were further discussed.

FinFET technology compared with planar have an increased sensitivity to single-event latch-up. TCAD simulation demonstrates that the reduction in width of MOSFET, thickness of shallow trench isolation (STI) and nMOS-to-pMOS lateral spacing will reduce the holding voltage, critical charge and increase the current gain of parasitic CMOS Silicon Controlled Rectifier (SCR). Through circuit analysis, it found that the change of parasitic vertical and horizontal resistance is mainly responsible for aforementioned phenomena. In addition, we found that the common protective measures such as guard rings spacing and epitaxial substrate become increasingly difficult. Based on the current preventive methods, we think that appropriate increasing the doping depth or the width of guard rings will improve protection from Single-Event Latch-up (SEL). Moreover, we verify the effectiveness of our methods by TCAD simulation and discuss the feasibility.

Geant4 Monte Carlo simulation results of the single event upset (SEU) induced by protons with energy ranging from 0.3 MeV to 1 GeV are reported. The SEU cross section for planar and three-dimensional (3D) die-stacked SRAM are calculated. The results show that the SEU cross sections of the planar device and the 3D device are different from each other under low energy proton direct ionization mechanism, but almost the same for the high energy proton. Besides, the multi-bit upset (MBU) ratio and pattern are presented and analyzed. The results indicate that the MBU ratio of the 3D die-stacked device is higher than that of the planar device, and the MBU patterns are more complicated. Finally, the on-orbit upset rate for the 3D die-stacked device and the planar device are calculated by SPACE RADIATION software. The calculation results indicate that no matter what the orbital parameters and shielding conditions are, the on-orbit upset rate of planar device is higher than that of 3D die-stacked device.

Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application of FinFET ultra large-scale integrated circuits (ULSI). Picosecond pulsed laser and high energy heavy ions were employed for irradiation. Before the tests, SRAM-based configure RAMs (CRAMs) were initialized and configured. The 100% embedded block RAMs (BRAMs) were utilized based on the Vivado implementation of the compiled hardware description language. No hard error was observed in both the laser and heavy-ion test. The thresholds for laser-induced single event upset (SEU) were ~3.5 nJ, and the SEU cross-sections were correlated positively to the laser&rsquo, s energy. Multi-bit upsets were measured in heavy-ion and high-energy laser irradiation. Moreover, latch-up and functional interrupt phenomena were common, especially in the heavy-ion tests. The single event effect results for the 16 nm FinFET process were significant, and some radiation tolerance strategies were required in a radiation environment.

The radiation effects of magnetic tunnel junction (MTJ) in a 180 nm Magnetoresistive Random Access Memory (MRAM) were investigated at the condition of the high heavy ion fluence (up to 1010 ions·cm−2) and high gamma-ray dose (up to 15 Mrad(Si)), respectively. The Hard Bit Error (HBE) was only observed when the energy of 181Ta ions was larger than 95.8 MeV under the ion fluence of 109 ions·cm−2 (~13 ions·bit−1). For gamma-ray exposure, no obvious effects were observed in devices. The HBE counts induced by 181Ta ions have a strong dependence on ion energy and cumulative fluence. In addition, the annealing characteristics of HBE after heavy ion irradiation at room temperature were also observed. It is found that the high ambient temperature is able to accelerate this annealing process. Monte Carlo simulation by using TRIM program revealed that the displacement damages induced by heavy ions were mainly located in the insulating layer of MTJ, which is responsible for the occurrence of HBE.

FDSOI technology has attracted considerable interests in space application due to its inherent high radiation resistance. An SEU hardened 8T SRAM cell is proposed and implemented in a test memory chip with advanced 22 nm UTBB FDSOI technology. Heavy ion experimental results show that the threshold LET of SEU for proposed 8T structure cell is up to ~24 MeV·cm2·mg−1 and less dependences of upset on data pattern and test modes are observed. Moreover, multiple bit upsets are not appeared in bitmap analysis results even under effective LET values at ~129 MeV·cm2·mg−1. The Pbb body biasing shows low influence on SEU rates in irradiation test, while the Nbb body biasing has ability to adjust the SEU sensitivity in a certain range. The error rate prediction indicates that this nanoscale FDSOI hardened SRAM is suitable for space application in harsh radiation environment.