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A Rigaku XSPA-500k detector was evaluated and its performance characterized on the Metrology beamline at Synchrotron SOLEIL together by the SOLEIL Detector Group, AGH-UST and Rigaku., Hybrid photon counting (HPC) detectors are widely used at both synchrotron facilities and in-house laboratories. The features of HPC detectors, such as no readout noise, high dynamic range, high frame rate, excellent point spread function, no blurring etc. along with fast data acquisition, provide a high-performance detector with a low detection limit and high sensitivity. Several HPC detector systems have been developed around the world. A number of them are commercially available and used in academia and industry. One of the important features of an HPC detector is a fast readout speed. Most HPC detectors can easily achieve over 1000 frames s−1, one or two orders of magnitude faster than conventional CCD detectors. Nevertheless, advanced scientific challenges require ever faster detectors in order to study dynamical phenomena in matter. The XSPA-500k detector can achieve 56 kframes s−1 continuously, without dead-time between frames. Using ‘burst mode’, a special mode of the UFXC32k ASIC, the frame rate reaches 1 000 000 frames s−1. XSPA-500k was fully evaluated at the Metrology beamline at Synchrotron SOLEIL (France) and its readout speed was confirmed by tracking the synchrotron bunch time structure. The uniformity of response, modulation transfer function, linearity, energy resolution and other performance metrics were also verified either with fluorescence X-rays illuminating the full area of the detector or with the direct beam.

Presents information on the European Summit on Solid-State Device and Circuit Research: Double Conference.

Semiconductor strip sensors applied as solid-state radiation or particle detectors can be used in radiation detection and measurement for various applications in particle physics experiments, X-ray imaging (e.g. medical), or material science. The X-ray imaging devices with spectroscopic and position resolution features are a very important research topic at many institutes and companies worldwide. Short strip silicon detectors are good candidates for X-ray spectroscopy, because of their relatively small capacitance and leakage current. If additionally, strip pitch is below 100 μm, then the high spatial resolution is also possible. In this paper, the analysis and noise optimization of the read-out electronics for short silicon strip detectors with Charge Sensitive Amplifier (CSA) and shaping amplifier (shaper) is presented. The CSA is optimized for the detector capacitance of around 1.5 pF, and the shaper nominal peaking time is about 1 μs (controlled by the sets of switches). We take into account the sources of noise in a radiation imaging system (current parallel noise, voltage series noise, and 1/f or flicker series noise) both internal (related to the front-end electronics itself) but also external, stemming from a sensor, interconnect, or printed circuit board parasitic components. We target the noise level below 40 el. rms, considering low power consumption (a few mW) and limited channel area.

We report on the design of an active feedback circuit for charge sensitive amplifiers used for reading out hybrid pixel detectors. The predominant advantages of the proposed feedback over the existing solutions are its low noise, stability, and tunability. In addition, the circuit occupies small silicon area, which is crucial for hybrid pixel detectors. This paper presents both the mathematical analysis of the proposed circuit and measurement results obtained with the test structure.

Spectrally selective X-ray imaging provides improved material and tissue discrimination in comparison with the state-of-the-art dual energy technologies that are commonly used in medical, industrial, and security applications. Cadmium telluride (CdTe)- and cadmium zinc telluride (CdZnTe)-based line scanners and small size two-dimensional X-ray sensors are emerging to the market, but the need for large-scale panels is axiomatic. In this study, a seamless CdTe tile was developed that enables the implementation of large-sized, energy selective X-ray detector panels. The developed tile consists of a $64\times64$ pixel array (with $150~\mu \text{m}$ pitch) with a necessary substrate, ASIC, and CdTe crystal. The performance of the constructed seamless tile was characterized by focusing on spectral resolution and stability. In addition, a simple pixel trimming method that automates the equalization of each energy selective pixel was developed and analyzed. The obtained results suggest that the proposed concept of seamless (tileable) detector structures is a feasible approach to scale up panel sizes. The seamless tile shows comparable spectral resolution and stability performance with commercial CdTe sensors. The effect of tile to tile variation, the realization of a large-scale panel, as well as the charge sharing performance were left out of the scope and are to be studied in the next phase.

We present the CBM physics performance study for measurements of the higher order cumulants of the net-proton multiplicity distributions. These observables are proxy for net-baryon fluctuations and are commonly used to study the phase structure of QCD phase diagram. The simulation is done for $Au+Au$ collision at beam kinetic energy $E_{lab} = 10$ AGeV. The cumulants of net-proton distributions have been calculated at midrapidity ($|��y| =1$) for the transverse momentum range $0.2 < p_T < 2.0$ GeV/c. The centrality dependence of cumulants of net-proton upto order four is presented. The efficiency and detector effects are corrected using unfolding techniques. This work shows that the higher order cumulants of net-proton can be measured using the CBM detector., Proceedings of the XXVIII th International Conference on Ultrarelativistic Nucleus-Nucleus Collisions (Quark Matter 2019), Wuhan, China, November 3-9 2019

This paper presents the design of a PXF40—an ultrafast single photon-counting (SPC) readout front-end electronics implemented in a CMOS 40-nm technology dedicated to hybrid pixel detectors. The prototype application specific integrated circuit core is a matrix of 432 pixels ( $24\times 18$ ) with a $100\,\,\mu \text {m}\times 100\,\,\mu \text{m}$ size. The single processing channel consists of a charge-sensitive amplifier (CSA), a discriminator, and a 24-bit counter with logic circuitry. The input signal is amplified and formed only by the CSA stage. Depending on the CSA input transistor current value, it can operate in two modes: FAST and FAST_HC with higher current. The measured power dissipation per channel $P = 45 \,\,\mu \text{W}$ and noise $\text {ENC} = 212\,\, \text {e}^{-}$ rms for the FAST mode, while $P=100\,\,\mu \text{W}$ and ENC = 185 e− rms for the FAST_HC mode, respectively. The readout chip can count up to 1.2 Gcps/mm2 based on 10% dead-time loss input rate parameter, which is currently the fastest SPC-based solution.

An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X-ray photons. Activation of groups of pixels, comparisons of peak amplitudes of pulses within an active neighborhood and finally latching of the results of these comparisons constitute the three procedural steps of the algorithm. A grouping of pixels to one virtual pixel , that recovers composite signals and event driven strobes, to control comparisons of fractional signals between neighboring pixels are the actuators of the algorithm. The circuitry necessary to implement the algorithm requires an extensive inter-pixel connection grid of analog and digital signals, that are exchanged between pixels. A test-circuit implementation of the algorithm was achieved with a small array of $32\times 32$ pixels and the device was exposed to an 8 keV highly collimated to a diameter of 3- $\mu \text{m}$ X-ray beam. The results of these tests are given in this paper assessing physical implementation of the algorithm.

X-ray imaging of moving objects using line detectors remains the most popular method of object content and structure examination with a typical resolution limited to 0.4–1 mm. Higher resolutions are difficult to obtain as, for the detector in the form of a single pixel row, the narrower the detector is, the lower the image Signal to Noise Ratio (SNR). This is because, for smaller pixel sizes, fewer photons hit the pixel in each time unit for a given radiation intensity. To overcome the trade-off between the SNR and spatial resolution, a two-dimensional sensor, namely a pixel matrix can be used. Imaging of moving objects with a pixel matrix requires time-domain integration (TDI). Straightforward TDI implementation is based on the proper accumulation of images acquired during consecutive phases of an object’s movement. Unfortunately, this method is much more demanding regarding data transfer and processing. Data from the whole pixel matrix instead of a single pixel row must be transferred out of the chip and then processed. The alternative approach is on-chip TDI implementation. It takes advantage of photons acquired by multiple rows (a higher SNR), but generates similar data amount as a single pixel row and does not require data processing out of the chip. In this paper, on-chip TDI is described and verified by using a single photon counting two-dimensional (a matrix of 128 × 192 pixels) CdTe hybrid X-ray detector with the 100 µm × 100 µm pixel size with up to four energy thresholds per pixel. Spatial resolution verification is combined with the Material Discrimination X-ray (MDX) imaging method.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operation of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- $\mu \text{m}$ -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.