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Your search keyword '"Paul H. J. Kelly"' showing total 238 results
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238 results on '"Paul H. J. Kelly"'

1. Convolutional kernel function algebra

Author

Edward Stow and Paul H. J. Kelly

Subjects
convolution, stencil, compiler, Focal-Plane Sensor-Processor, algebra, optimization, Electronic computers. Computer science, QA75.5-76.95
Abstract

Many systems for image manipulation, signal analysis, machine learning, and scientific computing make use of discrete convolutional filters that are known before computation begins. These contexts benefit from common sub-expression elimination to reduce the number of calculations required, both multiplications and additions. We present an algebra for describing convolutional kernels and filters at a sufficient level of abstraction to enable intuitive common sub-expression based optimizations through decomposing filters into smaller, repeated, kernels. This enables the creation of an enormous search space of potential implementations of filters via algebraic manipulation. We demonstrate how integral image and sliding window optimizations can be expressed in the context of common sub-expression elimination as well as show the direct use case for this algebra in massively SIMD multiply-free contexts such as in cellular processor arrays. We then show that this algebra is general enough to express and optimize kernels that use non-standard semi-rings to enable shortest path algorithms.

Published
2022
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25. Identification and Classification of Off-Vertex Critical Points for Contour Tree Construction on Unstructured Meshes of Hexahedra

Author

Marius Klaus Koch, Paul H. J. Kelly, Peter E. Vincent, Engineering & Physical Science Research Council (EPSRC), and The Leverhulme Trust

Subjects
Technology, Vertex (computer graphics), critical points, Computer science, Context (language use), Topology, Asymptotic decider, hexahedra, 0801 Artificial Intelligence and Image Processing, Polygon mesh, Point (geometry), Faces, Buildings, Visualization, 0802 Computation Theory and Mathematics, Science & Technology, Inspection, Isosurface, Isosurfaces, Software Engineering, Computer Science, Software Engineering, Computer Graphics and Computer-Aided Design, contour tree, Face (geometry), Computer Science, Signal Processing, Three-dimensional displays, Computer Vision and Pattern Recognition, Hexahedron, Element (category theory), Algorithm, Software
Abstract

The topology of isosurfaces changes at isovalues of critical points, making such points an important feature when building contour trees or Morse-Smale complexes. Hexahedral elements with linear interpolants can contain additional off-vertex critical points in element bodies and on element faces. Moreover, a point on the face of a hexahedron which is critical in the element-local context is not necessarily critical in the global context. In ‘`Exploring Scalar Fields Using Critical Isovalues’' Weber et al. introduce a method to determine whether critical points on faces are also critical in the global context, based on the gradient of the asymptotic decider in each element that shares the face. However, as defined, the method of Weber et al. contains an error, and can lead to incorrect results. In this work we correct the error.

Published
2022

26. Precise event sampling‐based data locality tools for AMD multicore architectures

Author

Muhammad Aditya Sasongko, Milind Chabbi, Paul H. J. Kelly, and Didem Unat

Subjects
Computational Theory and Mathematics, Computer Networks and Communications, Software, Computer Science Applications, Theoretical Computer Science
Abstract

We propose COMDETECTIVE+, an inter-thread communication analyzer, and REUSETRACKER+, a reuse distance analyzer, that leverage the hardware features in AMD processors to support low-overhead profiling. Both tools employ the instruction-based sampling (IBS) facility and debug registers in AMD processors to detect inter-thread communication and data reuse. Different from prior arts, COMDETECTIVE+ differentiates the communication into true and false sharing, and REUSETRACKER+ measures reuse distance in private and shared caches by also considering cache line invalidation with low overhead. Both tools can attribute the communications and reuses to source code lines. To our knowledge these tools are two of the few profiling tools designed specifically for AMD x86 architectures using IBS. Our tools are timely and relevant considering the rise in numbers of AMD processor based data centers and HPC systems. We perform experiments to evaluate the accuracy and overheads of the proposed tools on an AMD machine with two-socket EPYC 7352 processors. COMDETECTIVE+ exhibits high accuracy while introducing 5.14× runtime and 1.4× memory overheads. REUSETRACKER+ also displays high accuracy, which is 95%, with 11.76×runtime and 1.46× memory overheads. These overheads are much lower than the overheads of existing simulators and code instrumentation-based tools. Lastly, we demonstrate the usage of the tools by having COMDETECTIVE+ and REUSETRACKER+ facilitate the code refactoring of two data mining benchmarks to improve their performance by up to 29%.

Published
2023

27. Precise event sampling on AMD versus intel: quantitative and qualitative comparison

Author

Muhammad Aditya Sasongko, Milind Chabbi, Paul H J Kelly, and Didem Unat

Subjects
Computational Theory and Mathematics, Hardware and Architecture, Signal Processing
Abstract

Precise event sampling is a profiling feature in commodity processors that can sample hardware events and accurately locate the instructions that trigger the events. This feature has been used in a large number of tools to detect application performance issues. Although precise event sampling is readily supported in modern multicore architectures, vendor supports exhibit great differences that affect their accuracy, stability, overhead, and functionality. This work presents the most comprehensive study to date on benchmarking the event sampling features of Intel PEBS and AMD IBS and performs in-depth analysis on key differences through series of microbenchmarks. Our qualitative and quantitative analysis shows that PEBS allows finer-grained and more accurate sampling of hardware events, while IBS offers richer set of information at each sample though it suffers from lower accuracy and stability. Moreover, OS signal delivery, which is a common method used by the profiling software, introduces significant time overhead to the original overhead incurred by the hardware mechanisms in both PEBS and IBS. We also found that both PEBS and IBS have bias in sampling events across multiple different locations in a code. Lastly, we demonstrate how our findings on microbenchmarks under different thread counts hold for a full-fledged profiling tool that runs on the state-of-the-art Intel and AMD machines. Overall our detailed comparisons serve as a great reference and provide invaluable information for hardware designers and profiling tool developers.

Published
2023

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