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For the first time halfnium oxide (HfO2) is being incorporated in the dual‐k spacers and has been used in bulk planar junctionless transistor (BPJLT). It has been found that incorporating HfO2 in spacers not only improves the electrostatic integrity but also improves digital/analogue circuit performance of the BPJLT. Further, the increased effective gate length due to fringing electric field through HfO2 to thin body reduces OFF‐state leakage, subthreshold swing and drain‐induced barrier lowering by ∼60, ∼15 and ∼30%, respectively. Although the presence of HfO2 inner spacer layer at source/drain increases the parasitic capacitances, the significant improvement in ON‐state drive current reduces the intrinsic gate delay of the device. Further, the analogue circuit figures of merit such as transconductance, transconductance generation factor and the intrinsic gain of the proposed device are found to be significantly improved over the conventional BPJLT device. The mixed mode device/circuit simulation results of an inverter and the common source amplifier show that leakage power dissipation, propagation delay and the open‐circuit voltage gain of the proposed device are improved significantly over the conventional BPJLT device. The fabrication process flow of this novel device has also been proposed. [ABSTRACT FROM AUTHOR]

Abstract: In this paper CMOS logic circuit performance of dopant-segregated Schottky barrier (DSSB) SOI and δ-doped partially insulated DSSB SOI (DSSB Pi-OX-δ) MOSFETs has been explored by extensive mixed-mode device/circuit simulations. It has been found that, the presence of partial buried oxide and δ-doping in an n-channel and p-channel DSSB Pi-OX-δ MOSFETs not only suppresses the off-state leakage, short-channel effects, self-heating effect and the process induced threshold voltage variability but also improves the on-state drive current of the devices. Further, although switching energy in the CMOS inverter, NAND and NOR gates based on DSSB SOI and DSSB Pi-OX-δ MOSFETs is almost equal, static power dissipation and propagation delay in the logic gates based on DSSB Pi-OX-δ MOSFET are reduced by ∼75% and ∼20% respectively over the logic gates based on DSSB SOI device. Thus, employing partial buried oxide and δ-doping under the channel of DSSB SOI MOSFET not only eliminates the potential weaknesses of this device but also makes it a suitable candidate for nanoscale CMOS logic circuits. [Copyright &y& Elsevier]