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In this letter, the modeling and design of a low-power, compact folded cascode operational amplifier with high immunity to electromagnetic interference (EMI) is presented. The insights derived from the modeling of parameters $V_{gsi}$ , $V_{sbi}$ , and $V_{dsi}$ of the first-stage folded cascode OpAmp with channel length modulation are employed in designing the proposed compact folded cascode OpAmp with 23% reduction in power and 10% reduction in area when compared to the robust folded cascode OpAmp. In addition, a comprehensive comparison of the proposed compact folded cascode OpAmp, classical folded cascode OpAmp, and the robust folded cascode OpAmp is presented when each of these OpAmps are subjected to an EMI of 1.7 Vpp. The postlayout simulation results show that the maximum EMI-induced output offset voltage for the compact folded cascode OpAmp is 6.6 mV over a wide range of frequencies from 1 MHz to 1 GHz by keeping the main specifications intact as that of a robust folded cascode OpAmp. [ABSTRACT FROM AUTHOR]

Summary: In this work, a robust, low‐power, widely linear multiphase clock generation and multiplying delay‐locked loop (MPCG‐MDLL) architecture is realized, using a new differential charge‐mode delay element circuit topology. The heart of any MPCG‐MDLL architecture is the delay element, and hence, the characteristics of the delay element influence the overall performance of the MPCG‐MDLL, in terms of its specifications such as peak‐to‐peak jitter, lock range, delay range, control voltage range, and power consumption. The proposed eight‐phase MPCG‐MDLL along with the charge‐mode delay element outperforms the conventional MPCG‐MDLLs that deploy delay elements such as a current‐starved inverter (CSI), wide‐range CSI, triply controlled delay cell, digital‐controlled delay element, and the like. The eight‐phase MPCG‐MDLL along with the new charge‐mode delay element circuit topology is implemented in 1.2‐V, 65‐nm CMOS technology. The performance results show that the eight‐stage delay line has a delay range from 640 to 960 ps over the rail‐to‐rail control voltage range. The implemented MPCG‐DLL is robust over process, voltage, and temperature (PVT) corners and exhibits a lock range of 400 MHz and a peak‐to‐peak jitter of less than 60 fs for all the DLL output phases and peak‐to‐peak jitter of 0.54 and 1.24 ps for the synthesized 5‐GHz clocks for an input reference clock frequency of 1.25 GHz. The MPCG‐MDLL consumes 4.74 mW of power and occupies an area of 0.017 mm2. [ABSTRACT FROM AUTHOR]