221 results on '"Parvais, B."'
Search Results
2. High Performance mm Wave AlN/GaN MISHEMTs on 200 mm Si Substrate
3. A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability
4. The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits
5. Thermal Modelling of GaN & InP RF Devices with Intrinsic Account for Nanoscale Transport Effects
6. Comprehensive Investigations of HBM ESD Robustness for GaN-on-Si RF HEMTs
7. III-V/III-N technologies for next generation high-capacity wireless communication
8. Back Barrier Trapping Induced Resistance Dispersion in GaN HEMT: Mechanism, Modeling, and Solutions
9. FinFETs and Their Futures
10. III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance
11. Low-Voltage Scaled 6T FinFET SRAM Cells
12. (Invited) Defect Engineering for Monolithic Integration of III-V Semiconductors on Silicon Substrates
13. Modeling the SOI MOSFET nonlinearities. An empirical approach
14. Substrate effects in GaN-on-Si HEMT technology for RF FEM applications
15. III-V on a Si platform for the next generations of communication systems
16. Environmental Impact of CMOS Logic Technologies
17. Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors
18. Interpretation and modelling of dynamic-RON kinetics in GaN-on-Si HEMTs for mm-wave applications
19. Substrate effects in GaN-on-Si HEMT technology for RF FEM applications
20. Evidence of Tunneling Driven Random Telegraph Noise in Cryo-CMOS
21. Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
22. ESD HBM Discharge Model in RF GaN-on-Si (MIS)HEMTs
23. Impact of III-N buffer layers on RF losses and harmonic distortion of GaN-on-Si Substrates
24. Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
25. Transistor modelling for mm-Wave technology pathfinding
26. Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing
27. Understanding the memory window in 1T-FeFET memories: a depolarization field perspective
28. Transistor modelling for mm-Wave technology pathfinding
29. Impact of III-N buffer layers on RF losses and harmonic distortion of GaN-on-Si Substrates
30. Gate voltage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices
31. Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics
32. On the impact of buffer and GaN-channel thickness on current dispersion for GaN-on-Si RF/mmWave devices
33. A BSIM-Based Predictive Hot-Carrier Aging Compact Model
34. Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies
35. GaN on Si: substrate RF modelling
36. Impact of fin width on digital and analog performances of n-FinFETs
37. Parasitic subthreshold drain current and low frequency noise in GaN/AlGaN metal-oxide-semiconductor high-electron-mobility field-effect-transistors
38. Introducing 2D-FETs in Device Scaling Roadmap using DTCO
39. CMOS Cryo-Electronics for Quantum Computing
40. Substrate RF Losses and Non-linearities in GaN-on-Si HEMT Technology
41. DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies
42. GaN-on-Si mm-wave RF Devices Integrated in a 200mm CMOS Compatible 3-Level Cu BEOL
43. From 5G to 6G: will compound semiconductors make the difference?
44. Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs
45. FinFETs and Their Futures
46. Scalable and multibias high frequency modeling of multi-fin FETs
47. AlGaN/GaN MISHEMT analysis from an analog point of view up to 150°C
48. Low-Frequency Noise Investigation of GaN/AlGaN Metal–Oxide–Semiconductor High-Electron-Mobility Field-Effect Transistor With Different Gate Length and Orientation
49. 3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
50. Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.