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In many refrigeration and air-conditioning systems, the automatic controller in electronic expansion valves have been employed as a component responsible for controlling the valve opening so that the superheat at the outlet of the evaporator remains within the desired limits. In some of these controllers, the control parameters are tuned once for a certain operating point and remain unaltered, even when the operating conditions change, unless the operator changes it manually. For a strongly nonlinear plant with a dramatically time varying characteristics, linear time invariant (LTI) prediction accuracy might degrade significantly that the performance of traditional Model Predictive Controller (MPC) becomes unacceptable. This work presents an Adaptive-Model Predictive Control (AMPC) mechanism to address this degradation where the parameters are tuned continuously through recursive estimation and update approaches, making the MPC insensitive to prediction errors and to achieve the optimal superheat response. Moreover, an adaptive setpoint hunting algorithm is implemented so that the system achieves stability and improves energy efficiency simultaneously.

In many refrigeration and air-conditioning systems, the automatic controller in electronic expansion valves have been employed as a component responsible for controlling the valve opening so that the superheat at the outlet of the evaporator remains within the desired limits. In most of these controllers, the control parameters are tuned once for a certain operating point and remain unaltered even when the operating conditions change. For a strongly nonlinear plant with a dramatically time varying characteristics, linear time invariant(LTI) prediction accuracy might degrade significantly that the performance of traditional model predictive controller(MPC) becomes unacceptable. This work presents an Adaptive-Model Predictive Control mechanism to address this degradation where the parameters are tuned continuously through recursive estimation and update approaches, making MPC insensitive to prediction errors, so as to achieve the optimal superheat output.

In this paper, the mass optimization of four bar linkages is carried out using genetic algorithms (GA) with single and dual constraints. The single constraint of bending stress and the dual constraints of bending and buckling stresses are imposed. From the movement response of the bar linkage mechanism, the analysis of the mechanism is developed using the combination of kinematics, kinetics, and finite element analysis (FEA). A penalty-based transformation technique is used to convert the constrained problem into an unconstrained one. Lastly, a detailed comparison on the effect of single constraint and of dual constraints is presented.

Thermal management of device-level packaging continues to present many technical challenges in the electronics industry. In a device/heat sink assembly, the highest resistance to heat flow typically comes from the thermal interface material (TIM). The thermal conductivities of TIMs remain in the range of 1-4 W/mK due to the properties and structure of small dispersed solids in polymer matrices. As a result of the rising design power and heat flux at the silicon die, new ways to improve the effective in situ thermal conductivity of interface materials are required. This paper analyzes a unique TIM enhanced with ultrahigh-density wafer-level thin film-compliant interconnects referred to as smart three axis compliant (STAC) interconnects. MEMS technology is used to directly fabricate STAC interconnects onto a silicon wafer and embed them into the TIM to provide an enhanced conductive path between the die/package and the heat sink. Here, results from a theoretical analysis of the thermal conduction in a TIM embedded with STAC interconnects are reported. The objective of the study is to provide comprehensive design strategies for effective implementation of this type of TIM for specific applications. Parametric studies are performed to examine the thermal resistance of the microinterconnect-enhanced TIM for varying materials, configurations, and geometry of the microinterconnects. A periodic element model of a chip-TIM configuration with top heat sink is used to evaluate the conductive effect of the microinterconnects. In addition, an investigation of the conductive transport in a more complicated chip stack is considered. A 3-D thermal analysis is conducted for a multichip stack package with and without through-silicon vias. The numerical results show that the microinterconnects significantly improve the thermal performance of the TIM. Finally, further steps toward achieving a chip-level design optimization and fabrication process using a STAC microinterconnect structured TIM is proposed.

The present trend in electronics packaging is the stacking of die at the wafer or chip level. However to ensure stacked chip packages maintain overall low height and weight package profile, silicon wafers have to undergo extensive wafer thinning processes. In this work, a systematic approach to thinning silicon wafers down to sub-40μm in thickness is presented. This paper will cover a detailed three stage wafer thinning method, which includes the mechanical back-lapping method for the bulk removal process and a combination of mechanical polishing and spin-spray wet chemical etch method for the fine removal wafer thinning process. The results will show that by just utilizing the mechanical back-lapping and mechanical polishing process the wafers can be easily thinned from 380μm to less than 50μm with ±2.5μm Total Thickness Variation (TTV). These back-lapped wafers are then further thinned by the spin-spray etching method to achieve final wafer thickness of less than 40μm. The paper will also show that by utilizing a modified carrier wafer, the handling of these sub-40μm ultra-thin wafers do not require custom made tools and can be easily integrated into existing wafer handling tools.

Genetic Algorithms (GA) are adaptive search algorithms based on the theory of natural selection and survival of the fittest. In this study, GA was used to derive a thermal compact model of a micro lead frame package. The GA derived model was then used to compute the junction temperature (T/sub j/) of the package for various boundary conditions. The results obtained were checked against simulation results of a detailed thermal model and were found to be within /spl plusmn/1.5% of error. Computational time taken by the detailed finite element model required approximately 4 min whereas the GA derived model took less than 35 s to generate the T/sub j/ of the package. Further, the study shows the feasibility and potential of applying GA as a powerful tool for optimization.

Solders have been utilized extensively in the MEMS packaging industry to create vacuum or hermetic seals in a variety of applications. MEMS technology is finding applications in wide range of products like pressure sensors, actuators, flow control devices etc. For many harsh low temperature environment applications, like commercial refrigeration systems, MEMS based pressure sensors and flow actuators are directly mounted on to metal substrates using solders to create hermetic sealing. Solders attaching silicon devices directly to metal substrates may be subjected to very high thermal stresses due to significant difference in thermal expansion coefficients during chip operation or environment temperatures. In this paper, case study of a high powered MEMS chip (referred in the paper as die) operating in a commercial refrigeration system is presented. Accelerated test method for qualifying solder joint for high pressure applications is briefly discussed. Lab experiments showing typical refrigeration cycle thermal load on solder joint are presented. Based on the study, concepts of die power toggling and power allocation towards enhancing hermetic solder joint reliability are discussed. Detailed numerical case studies are presented to quantify the improvement in solder joint reliability due to the proposed concept.

Thermal management of device level packaging continues to present many technical challenges. In the typical chip heat sink assembly, the highest resistance to heat flow comes from the thermal interface material (TIM). The thermal conductivities of TIMs remain in the range of 1-4 W/mK due to the properties and structure of small dispersed solids in polymer matrices. As a result of the rising design power and heat flux at the silicon die, new ways to improve the effective in situ thermal conductivity of interface materials are required. This paper will introduce a unique TIM enhanced with ultrahigh density wafer level thin film compliant interconnects named smart three axis compliant (STAC) interconnects. The MEMS technology based STAC interconnect is directly fabricated onto a silicon wafer and embedded into the TIM to provide an enhanced conductive path between the die/package and the heat sink. Numerical and analytical analyses of the thermal conduction in the TIM embedded with STAC interconnects are performed. The objective of the study is to provide comprehensive design strategies for effective implementation of this type of TIM for specific applications. Parametric studies are conducted to examine the thermal conductivity of the microinterconnect enhanced TIM for varying materials, configurations, and geometry of the microinterconnects. For the modeling, a periodic element model of chip-TIM configuration with top heat sink is developed and maximum temperatures are determined in order to evaluate the conductive effect of the microinterconnect. In addition, an investigation of the conductive transport in a more complicated chip stack is considered. A 3-D thermal analysis is conducted for a multi-chip stack package with and without through-silicon-vias. The numerical results show that the microinterconnects significantly improve the thermal performance of the TIM. Finally, further steps toward achieving a chip-level design optimization and fabrication process using microinterconnects structured TIM is proposed.

In this study, a hybridized neuro-genetic optimization methodology realized by embedding finite element analysis (FEA) trained artificial neural networks (ANN) into genetic algorithms (GA), is used to optimize temperature control in a ceramic based continuous flow polymerase chain reaction (CPCR) device. The CPCR device requires three thermally isolated reaction zones of 94 degrees C, 65 degrees C, and 72 degrees C for the denaturing, annealing, and extension processes, respectively, to complete a cycle of polymerase chain reaction. The most important aspect of temperature control in the CPCR is to maintain temperature distribution at each reaction zone with a precision of +/-1 degree C or better, irrespective of changing ambient conditions. Results obtained from the FEA simulation shows good comparison with published experimental work for the temperature control in each reaction zone of the microfluidic channels. The simulation data are then used to train the ANN to predict the temperature distribution of the microfluidic channel for various heater input power and fluid flow rate. Once trained, the ANN analysis is able to predict the temperature distribution in the microchannel in less than 20 min, whereas the FEA simulation takes approximately 7 h to do so. The final optimization of temperature control in the CPCR device is achieved by embedding the trained ANN results as a fitness function into GA. Finally, the GA optimized results are used to build a new FEA model for numerical simulation analysis. The simulation results for the neuro-genetic optimized CPCR model and the initial CPCR model are then compared. The neuro-genetic optimized model shows a significant improvement from the initial model, establishing the optimization method's superiority.

In this paper, detailed 3D FEM thermo-mechanical analysis is performed on a chip stack that utilizes the smart three axis compliant (STAC) interconnect, a TSV based ultra-high density compliant interconnect. These interconnects are microstructurally engineered to accommodate relative displacements between ultra-thin TSV based silicon chips and substrates to which they are bonded without transferring significant stress to the die itself. The paper will first cover 3D numerical model of the TiW bi-metal layer compliant beam built with opposing stresses to establish z-axis lift-height that compares well with analytical results. With this validated model, a force-deflection curve is established for a 125 mumtimes25 mumtimes0.8 mum TiW free beam with 1 GPa stress built into its two metal layers (-500 MPa in the bottom layer and +500 MPa in the top layer). This enables numerical characterization of the compliancy of a single interconnect. This analysis is followed by thermo-mechanical analysis of a unit cell STAC interconnect (TSV, copper bond pad and the compliant beam) built on a 50 mum thick silicon die. Particular attention is given to stresses formed in the TSV copper column when temperature is varied from -40degC to 150degC. Finally experimental results performed on a successfully fabricated STAC interconnect based Si-Glass stacked die is presented and a numerical model of this chip stack is built to capture the top ultra-thin glass die deformation when temperature is varied from 20degC to 130degC.

This paper described a novel smart three axis compliant (STAC) interconnect targeted to revolutionize chip-to-chip and chip-to-board high-density 3D integration for ultra-thin Si dies (les75mum) at the wafer level. The STAC interconnect is a three dimensionally compliant interconnect which allows stacked ultra-thin chips to move or flex freely during operation with negligible stress imposed on the die. The paper showed that these interconnects could accommodate mismatches of board or package coefficient of thermal expansion (CTE) from chip CTE. STAC interconnects were fabricated using MEMS technologies to support super-fine-pitch (ap20mum pitch) interconnection. These interconnects are batch processed and die containing them can be stacked either at the wafer-level or at the die-level

A thermal response model for designing thermal energy storage heatsink utilized for electronics cooling is developed in this paper. In this study, thermal energy storage (TES) heatsink made out of aluminum with paraffin as the phase change material (PCM) is considered. By using numerical simulation, stabilization time and maximum operating temperature to transition temperature difference is obtained for varying fin thicknesses, fin height, number of fins and PCM volume. The numerical simulation results were then compared with existing experimental work. The numerical results matched the melting temperature variation obtained by the experimental work. The validated numerical results are then used to train the artificial neural networks (ANN) to predict stabilization time and maximum operating temperature to transition temperature difference for new fin thicknesses, fin height, number of fins and PCM volume. Finally the optimization of the fin thickness, fin height, number of fins and PCM volume of the thermal energy storage heatsink is obtained by embedding the trained ANN as a fitness function into genetic algorithms (GA). The objective of optimization is to maximize stabilization time and to minimize maximum operating temperature to transition temperature difference. Finally the optimized results for the TES heatsink is used to build a new computer model for numerical analysis. The final optimized model results and the validated preliminary model results are then compared. The final results will show a significant improvement from the validated model. Further the study will show that by combining ANN and GA, a superior tool for optimization is realized.Copyright © 2005 by ASME

The current trend in wafer-level three-dimensional integration is by copper-filled through-silicon vias (TSVs) which considerably minimize signal transmission time due to the short wiring length required to integrate vertically stacked chips. However, the present wire bonding technology widely used in peripheral integration of stacked chips cannot integrate TSV based chip stacks. This article describes the fabrication methodology of a thin film compliant interconnect referred to as Smart Three Axis Compliant (STAC) interconnects which can be directly integrated onto TSV based chip stacks. These batch processed compliant interconnects are successfully fabricated utilizing microelectromechanical systems technology at the wafer level by magnetron sputtering oppositely stressed layers of TiW films. Once patterned and released, STAC interconnects easily achieve input/output counts of 104∕cm2 or greater, making it suitable to be directly integrated onto through-silicon-via based chip stacks.