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11. A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

17. 23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

19. Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM

22. 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

23. Robust Saturation Controller for the Stable LTI System with Structured Real Parameter Uncertainties

24. Robust Optimal Bang-Bang Controller Using Lyapunov Robust Stability Condition

25. An Improved Finite Difference Type Numerical Method for Structural Dynamic Analysis

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