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The physical implementation of reservoir computing (RC), a brain-inspired computing framework, is attracting increasing attention in various research fields owing to its capability of quick learning and the relatively simple training process. Although several physical RC models have been envisaged and realized, most of them require additional peripherals; it leads to an increase in the power consumption of the system. In this study, we propose a novel RC model that is based on an overdamped bistable system and exhibits a counter-intuitive phenomenon called stochastic resonance, through which it can transfer noise energy to the information-carrying signal to realize learning with a comparatively low power consumption. The proposed model also possesses the functional capability of filtering and amplification and thus does not require additional peripheral equipment. In order to prove the feasibility and determine the desired operation mode of the system, two basic benchmark tests, namely short-term memory and parity check tasks, were employed to assess the proposed model. The results verify that this work will potentially act as a stepping stone towards realizing even better low-power-consumption physical RC.

Emerging memory technologies rely on Multilevel Cells (MLC) to achieve high density; the use of multiple levels per cell allows storage of multiple bits, but it also reduces the margins and makes it error prone. Error control codes (including error correction and detection codes) can be used to protect MLC memories from errors; however, most existing coding schemes have been designed for traditional binary memories (so storing a single bit). In MLC memories, errors cause a change from a level to an adjacent level or to the next one (depending on the employed technology), so they are often referred to as limited magnitude errors. For a binary coding of levels to bits, these limited magnitude errors can corrupt several bits making traditional coding schemes inefficient. In this paper, error detection of MLC memories is considered when a binary encoding of levels to bits is used and two new schemes are proposed: One-Bit Parity (OBP) and Two-Bit Parity (TBP). The first scheme targets errors of magnitude-1 for detection using a single parity bit that checks only one bit per cell. The second scheme detects both magnitude-1 and -2 errors using only two parity bits. Both schemes are compared to existing alternatives, namely Gray coding combined with a single parity bit (GP) for OBP and Interleaved Parity (IP) for TBP. The results show that OBP reduces the encoding and error detection circuitry complexity and delay, while TBP additionally reduces the number of parity bits for some configurations. Therefore, OBP and TBP can be efficient alternatives for detection of limited magnitude errors in MLC memories that use a binary encoding of levels to bits.

When polar codes are decoded by the successive cancellation (SC) decoding algorithm, erroneously decoded non-frozen bits are caused by either channel noise or error propagation. SC-Flip algorithms aim to improve error performance by first identifying erroneous hard decisions due to channel noise and then flipping them during the decoding process to reduce error propagation. In existing SC-Flip algorithms, cyclic redundancy check (CRC) is used to check the decoded codeword to detect incorrect hard decisions. Differing from this detection approach based on CRC, we propose new SC-Flip decoders that take advantage of both the CRC and distributed parity checks (PCs) to detect, identify and flip erroneously decoded non-frozen bits. The proposed decoders terminate SC decoding early when a distributed PC is not satisfied. In addition, we propose a new metric to help locate the incorrect hard decisions. Finally, simulation results demonstrate that our SC-Flip decoders achieve better performance complexity tradeoffs than prior flipping algorithms, and approach the performance and complexity of the SC-Oracle algorithms.

The Low-Density Parity Check (LDPC) codes of Euclidean Geometry (EG) are encrypted and decrypted in numerous ways, namely Soft Bit Flipping (SBF), Sequential Peeling Decoder (SPD), Belief Propagation Decoder (BPD), Majority Logic Decoder/Detector (MLDD), and Parallel Peeling Decoder (PPD) decoding algorithms. These algorithms provide aextensive range of trade-offs between latency decoding, power consumption, hardware complexity-required resources, and error rate performance. Therefore, the problem is to communicate a sophisticated technique specifying the both soft and burst errors for effective information transmission. In this research, projected a technique named as Hybrid SBF (HSBF) decoder for EG-LDPC codes, which reduces the decoding complexity and maximizes the signal transmission and reception. In this paper, HSBF is also known as Self Reliability based Weighted Soft Bit Flipping (SRWSBF) Decoder. It is obvious from the outcomes that the proposed technique is better than the decoding algorithms SBF, MLDD, BPD, SPD and PPD. Using Xilinx synthesis and SPARTAN 3e, a simulation model is designed to investigate latency, hardware utilization and power consumption. Average latency of 16.65 percent is found to be reduced. It is observed that in considered synthesis parameters such as number of 4-input LUTs, number of slices, and number of bonded IOBs, excluding number of slice Flip-Flops, hardware utilization is minimized to an average of 4.25 percent. The number of slices Flip-Flops resource use in the proposed HSBF decoding algorithm is slightly higher than other decoding algorithms, i.e. 1.85%. It is noted that, over the decoding algorithms considered in this study, the proposed research study minimizes power consumption by an average of 41.68%. These algorithms are used in multimedia applications, processing systems for security and information.

Modern communication systems tend to use different channel codes to find a balance between communication speed and quality. Accordingly, the blind identification techniques of encoders have drawn much research interest. In this letter, we propose a blind identification scheme for the Low-Density Parity Check (LDPC) coded communication systems based on a known candidate set. The proposed scheme can adaptively adjust the length of the received sequence to approach an arbitrary probability of missed detection and false alarm for codes in the candidate set, where the latter probability has received little attention by the existing methods. On this basis, the proposed scheme can determine whether there are unknown codes in the received vector, which is useful in practical applications. The performance of the proposed scheme is investigated using system simulations.

Error-correcting codes (ECCs) are essential to improve the reliability of digital communication systems. ECCs can detect or correct the errors by introducing and utilizing the systematic parity check bits, which however deteriorate the spectral efficiency of digital communication systems. In order to enhance the spectral efficiency, the used ECC may be blindly detected at the receiver. Also, blind detection of ECCs is important in the broadcasting systems. Recently, blind detection schemes of ECCs have been actively studied and most of them assume that the receiver knows which type of ECC, a block code or a non-block code, is used. However, in real situations, blind classification about whether the ECC is a block code or a non-block code should be performed first. In this paper, a blind classification scheme of ECCs in a noisy environment is proposed, which does not require the knowledge of parameters of the used ECC. The proposed scheme classifies whether the received bit-stream is encoded by an ECC or not, and if it is determined that the received bit-stream is encoded, the proposed scheme further classifies whether the used ECC is a block code or a non-block code. Also, a novel rank calculation scheme of the intercepted matrix is proposed by performing a probabilistic analysis of random row permutation for the intercepted matrix. Based on this analysis, the minimum number of random row permutations is theoretically derived for guaranteeing correct rank calculation with probability at least $\beta $ . Through various simulations, it is shown that the proposed rank calculation and blind classification schemes outperform the existing rank calculation and blind classification schemes. Furthermore, it is verified that the performance gap between the proposed schemes and the existing schemes becomes larger as $\beta $ is increased.

Various document types play an influential role in a lot of our lives activities today; hence preserving their integrity is an important matter. Such documents have various forms, including texts, videos, sounds, and images. The latter types' authentication will be our concern here in this paper. Images can be handled spatially by doing the proper modification directly on their pixel values or spectrally through conducting some adjustments to some of the addressed coefficients. Due to spectral (frequency) domain flexibility in handling data, the domain coefficients are utilized for the watermark embedding purpose. The integer wavelet transform (IWT), which is a wavelet transform based on the lifting scheme, is adopted in this paper in order to provide a direct way for converting image pixels' integer values to integer coefficient values rather than floating point coefficients that could be produced by the traditional wavelet transform. This direct relation can enhance the processed image quality due to avoiding the rounding operations on the floating point coefficients. The well-known parity bit approach is also utilized in this paper as an authentication mechanism, where 3 secret parity bits are used for each block in an image which is divided into non-overlapped blocks in order to enforce a form of fragile watermark approach. Thus, any alteration in the block pixels could cause the adopted (even) parity to be violated. The fragile watermarking is achieved through the modification of least significant bits ((LSBs) of certain frequency coefficients' according to the even parity condition. In spite of this image watermarking operation, the proposed method is efficient. In order to prove the efficiency of our proposed method, it was tested against standard images using measurements like peak signal to noise ratio (PSNR) and structural similarity index (SSIM). Experiments showed promising results; the method preserves high image quality (PSNR≈ 44.4367dB, SSIM≈ 0.9956) and good tamper detection capability.

We propose new fault-tolerant architectures, which, in contrast to the well-known double and triple modular redundancy architectures, include only one copy of the original circuit. In the new architectures, a signal error detection circuit is used to select the functions to be corrected. The circuit is built on the basis of the Boolean complement method with parity check of calculations. A generalized architecture with Boolean complement based signal correction is presented. This architecture permits one to design the simplest fault-tolerant circuits. Algorithms for designing signal error detection circuits, as well as examples of their application, are given.

In this paper, we focus on novel designs for digital code converter and parity generator circuits in quantum-dot cellular automata (QCA) technology, which is transistor less computation approach and encodes binary information through the configuration of charges among quantum dots. In existing works, code converters and parity generators have been designed using majority gate and inverter-based XOR gates that is the basic structure of these circuits. However, our proposed designs use explicit cell interaction-based XOR gate to designing a compact form of QCA circuits. As a result, novel designs for generating parity bit, Binary to Gray, Gray to Binary code converter are presented with low complexity. Moreover, we will first demonstrate the bifunctional parity generator in QCA. The correct operation of the structures has been verified using the QCADesigner tool. A structural comparison was made with previous works and found that the proposed designs have significant improvements over existing ones.

This paper proposes an approach to protect image content against malicious tampering based on watermarking technology. The watermark is composed of two kinds of check bits which are used for tampered region localization, and one recovery bit which is used for image recovery and is embedded into the three-Least Significant Bit planes of the original image. The first check bit is generated by applying the proposed Parity Check Bit Labeled method to each pixel, and the other is generated by employing hashing algorithm to each block after image decomposition. The superposition result detected from the two check bits contributes to lowering the probability of false-negative errors. Moreover, we propose a post-processing method Adaptive Structural Element Calculation which improves the accuracy of tamper detection result further. Experimental results show that our algorithm has good performance in keeping high quality of recovered image, and meanwhile improving the accuracy of tamper detection result.

We consider an iterative phase synchronization scheme based on maximum a posteriori probability algorithm. In classical approaches, the phase noise estimation model considers one sample per symbol at the channel and receiver. However, information theoretic studies suggested use of more than one sample per symbol at the channel and receiver for achieving higher performance. In this article, a soft-information aided iterative receiver is derived, which uses off-the-shelf blocks for detection and demodulation by keeping the complexity of the receiver acceptable. We consider here two samples per symbols at the channel and receiver in a pragmatic paradigm. It is shown that phase noise estimation can be significantly improved at the expense of modest processing overhead. Simulation results are presented for low-density parity check coded quadrature amplitude modulations. Our results show a significant performance improvement for strong phase noise values compared to classical receiver approaches.

Non-Orthogonal Multiple Access (NOMA) is an efficient multiple access scheme which augments the capacity and overall throughput in LTE and 5G networks. Tackling the high system throughput and device connectivity of multiple users with different channel state information is a key challenge at this juncture. The joint detection and decoding using parity check polar coding (PCPC) and the utilization of Sparse Code Multiple Access (SCMA) in Code domain NOMA improves throughput supporting an overloaded number of users. Also, Multiple-Input Multiple-Output (MIMO)-SCMA scheme has potential in providing spectrum and energy efficiency. MIMO-SCMA superimposes multiple users in the code domain and utilizes the channel gain difference between multiplexed users. Hence, this paper aims to propose a proficient code domain NOMA scheme, the PCPC SCMA multiplexed over Orthogonal Frequency Code Division Multiple Access (OFCDMA), implementing a joint detection and decoding with user scheduling. Signals of numerous users are superimposed and transmitted over a channel. At the receiver, Multi-User Detection (MUD) exploiting the Message Passing Algorithm (MPA) is used to identify the desired user. To ensure proper resource utilization of multiple data blocks, the users are scheduled by implementing the Invasive Weed Optimization (IWO) technique along with the MPA. The proposed scheme, which engages an IWO-MPA based MUD scheme, improves the convergence rate, in terms of the number of iterations thereby leading to lower complexity, as well as reduces the Bit Error Rate (BER). Computer simulations reveal that the proposed scheme achieves high spectrum and energy efficiency, higher throughput and overloaded user fairness compared with recent researches.

Classification is used in a wide range of applications to determine the class of a new element; for example, it can be used to determine whether an object is a pedestrian based on images captured by the safety sensors of a vehicle. Classifiers are commonly implemented using electronic components and thus, they are subject to errors in memories and combinational logic. In some cases, classifiers are used in safety critical applications and thus, they must operate reliably. Therefore, there is a need to protect classifiers against errors. The k Nearest Neighbors (kNNs) classifier is a simple, yet powerful algorithm that is widely used; its protection against errors in the neighbor computations has been recently studied. This paper considers the protection of kNNs classifiers against errors in the memory that stores the dataset used to select the neighbors. Initially, the effects of errors in the most common memory configurations (unprotected, Parity-Check protected and Single Error Correction-Double Error Detection (SEC-DED) protected) are assessed. The results show that surprisingly, for most datasets, it is better to leave the memory unprotected than to use error detection codes to discard the element affected by an error in terms of tolerance. This observation is then leveraged to develop Less-is-Better Protection (LBP), a technique that does not require any additional parity bits and achieves better error tolerance than Parity-Check for single bit errors (reducing the classification errors by 59% for the Iris dataset) and SEC-DED codes for double bit errors (reducing the classification errors by 42% for the Iris dataset). S. Liu and F. Lombardi would like to acknowledge the support of National Science Foundation, USA grants CCF-1953961 and 1812467, and P. Reviriego would like to acknowledge the support of the ACHILLES project PID2019-104207RB-I00 and the Go2Edge network RED2018-102585-T funded by the Spanish Ministry of Science and Innovation and by the Madrid Community research project TAPIR-CM P2018/TCS-4496.

Orthogonal time frequency space (OTFS) is being pursued in recent times as a suitable wireless transmission technology for use in high mobility scenarios. In this work, we propose nonorthogonal multiple acess (NOMA) based OTFS which may be called NOMA-OTFS system and evaluate its performance from system level and link level perspective. The challenge lies in the fact that while OTFS transmission technology is known for its resilience to high mobility conditions, while NOMA is known to yield high spectral efficiency in low mobility scenarios in comparison to orthogonal multiple access (OMA). We present a minimum mean square error (MMSE)- successive interference cancellation (SIC) based receiver for NOMA-OTFS, for which we derive expression for symbol-wise post-processing SINR in order to evaluate system sum spectral efficiency (SE). We develop power allocation schemes to maximize the sum SE in the high-mobility version of NOMA. We further design a realizable codeword level SIC (CWIC) receiver using LDPC codes along with MMSE equalization for evaluating link level performance of such practical NOMA-OTFS system. The system level and link level performance of the proposed NOMA-OTFS system are compared against benchmark OMA-OTFS, OMA-orthogonal frequency division multiplexing (OMA-OFDM) and NOMA-OFDM schemes. From system-level performance evaluation, we observe interestingly that NOMA-OTFS provides higher sum SE than OMA-OTFS. When compared to NOMA-OFDM, we find that outage SE of NOMA-OTFS is improved at the cost of decrease in mean SE. Whereas link-level results show that the developed CWIC based NOMA-OTFS receiver performs significantly better than NOMA-OFDM in terms of block error rate (BLER), goodput and throughput., Comment: 12 pages, 4 figures. Accepted for publication in IEEE Systems Journal

In cognitive radio context, the coding parameters are unknown at the receiver. The design of an intelligent receiver is essentially to identify these parameters from the received data blindly. In this paper, we are interested in the blind identification of binary linear block codes from received noisy data. In order to recognize the code length, the concept of the normalized column weight vector is defined and cosine similarity is used to measure the difference between linear block codes and random codes. Then, the correct code length could be obtained by finding the local minimum of cosine similarity. The proposed code length recognition method needs no prior knowledge about the codes, which results in completely blind identification. To reconstruct the parity check matrix, the concept of association rules mining is introduced to the problem of blind identification of channel codes for the first time. Furthermore, five criteria are proposed to reduce the redundant rules mined by the association rules mining algorithm and to recognize the parity check vectors effectively. Simulations show that the proposed two methods have excellent performance even in a high error rate transport environment. The performance comparisons with existing methods validate the advantages of our two proposed methods.

This paper attempts to propose a one-time pad block encryption using non-uniform cellular automata for the public cloud which satisfies avalanche diffusion and confusion properties. It is found tha...

As the density of flash memory is increasing to improve storage capacity, it also becomes more vulnerable to reading errors. Hence it is common practice to employ error-correcting codes, such as low-density parity check (LDPC) codes. To exploit the error-correcting capability of these codes, soft input must be provided to the decoder. This means that the flash memory controller needs to be able to provide reliability values, which is usually obtained through multiple ‘soft’ reads of the cells in the form of log-likelihood ratios (LLR). However finding these reliabilities with high accuracy is not easy with very few reads. In this brief we present a novel approach to estimate the LLRs based on a previous idea by Sharon et al. for regular LDPC codes. We present a low-complexity solution using machine learning and also an extension to irregular LDPC codes. A neural network is trained with offline data (simulated or measured) for a wide range of operating conditions and can then be applied to flash memory readings. By simulations we show that this provides good performance with only a small loss compared with genie-aided LLRs.

In this paper, the posterior probabilities of the low-density parity check (LDPC) coded bits are derived for the orthogonal frequency division multiplexing index modulation (OFDM-IM) system to reduce the implementation complexity of LDPC decoding without performance loss. Specifically, the complexity of LDPC decoding is reduced by decomposing the posterior probability of the coded bit into multiple likelihood probabilities, each of which is obtained for each subcarrier of the corresponding OFDM-IM subblock. The results of the complexity analysis indicate that the proposed approach significantly reduces the implementation complexity of LDPC decoding for OFDM-IM compared to the conventional approach. Furthermore, the simulation results confirm that the proposed approach provides the same bit error rate performance as the conventional approach.

A 60-GBaud intensity modulation and direct detection discrete Fourier transform spread (DFT-S) discrete multi-tone (DMT) transmission system employing low-density parity check- (LDPC-) encoded probabilistic shaping 16-ary quadrature amplitude modulation (PS-16QAM) is proposed and experimentally demonstrated. In contrast to classical probability-oriented PS schemes such as arithmetic distribution matching (ADM) and constant composition distribution matching (CCDM), the proposed one is performed based on a novel bit-weighted distribution matching (BWDM) algorithm having the advantage of simpler operations along with lower computation and hardware complexity, which merely relies on bit-class processing. As the key content of the BWDM, the bit weight intervention operation is utilized to enlarge the probability of bit ‘0’ in the first two out of four serial binary sequences before PS-16QAM mapping. Different from the labels indicating probability distribution in ADM and CCDM, the end product of the BWDM is a group of bits mapped from input data source, which can be seamlessly compatible with the following LDPC-based forward error correction. In our experiments, system performance is respectively investigated with three LDPC code rates (3/4, 5/6, and 9/10) as well as three PS parameter values ( k = 4, 5, and 7), which leads to various symbol probability distribution. Compared with standard uniformly-distributed 16QAM, up to 0.407-dB shaping gain can be achieved to approach Shannon limit in the low signal-to-noise ratio region. Moreover, the experimental results show that appreciable receiver power sensitivity improvement can be obtained by the PS-16QAM DMT based on BWDM over 2-km standard single-mode fiber for short-reach optical interconnection. Additionally, the reference-based pre-equalization is equipped to compensate for the high frequency loss by ultra-wide signal bandwidth.

Heat-assisted interlaced magnetic recording (HIMR) further increases recording density compared to heat-assisted magnetic recording due to the interlaced track layout. However, the smaller circular thermal profile of the top low-temperature-written tracks results in severe transition curvatures, which causes nonlinear distortions of the readback signal and degrades the bit error rate (BER) performance. Moreover, the increased recording density causes severe two-dimensional (2-D) intersymbol interference (ISI) along both down track and cross track directions. To mitigate the effect of nonlinear distortion and 2-D ISI in an HIMR system, we model a 2-D soft-transition, information-assisted, multitask neural network and modified Bahl–Cocke–Jelinek–Raviv (BCJR) detector (2DST-MTNN-MB) algorithm to detect three tracks simultaneously. The readback signal and 2-D soft-transition information are fed into the multitask neural network to obtain equalized signals and soft bit estimates of three tracks simultaneously. Then, the signal of the current track and soft estimates of the side tracks are embedded into the branch metrics of the modified BCJR detector for data detection, and the low-density parity check decoder is cascaded for error correction. The simulation results show that the 2DST-MTNN-MB algorithm provides 5.0 dB signal-to-noise ratio gains with reduced computation complexity compared with a single-track, single-task neural network and one-dimensional BCJR detector algorithm for the low-temperature-written track at channel bit density of 3.51 Tb/in2, thereby narrowing the gap of BER performance between high- and low-temperature-written tracks.

The paper proposes a method for designing self-checking pseudorandom number generators based on shift registers with linear and nonlinear feedbacks (LFSR and NLFSR, respectively). The concept of an (M + 1)-sequence generator is introduced for NLFSRs, which form sequences of the maximum possible length for a given generator bit width. The circuits of generators of (M – 1)- and (M – 3)-sequences have been modified in order to increase the length of the period of the generated sequences. Logical schemes of NLFSR self-control based on parity checking of PRNG states are presented.

Free space optical (FSO) communication systems provide wireless line of sight connectivity in the unlicensed spectrum, and wireless optical communication achieves higher data rates compared to their radio frequency (RF) counterparts. FSO systems are particularly attractive for last mile access problem by bridging fiber optic backbone connectivity to RF access networks. To cope with this practical deployment scenario, there has been increasing attention to the so-called dual-hop (RF/FSO) systems where RF transmission is used at a hop followed by FSO transmission to another. In this article, we study the performance of cooperative transmission systems using a mixed RF-FSO DF (decode and forward) relay using error-correcting codes including QC-LDPC codes at the relay level. The FSO link is modeled by the gamma-gamma distribution, and the RF link is modeled by the Additive White Gaussian Noise (AWGN) model. Another innovation in this article is the use of cooperative systems using a mixed FSO/RF DF relay using quasicyclic low-density parity check (QC-LDPC) codes at the relay level. We also use the space-coupled low-density parity check (SC-LDPC) codes on the same scheme to show its importance in cooperative optical transmission but also in hybrid RF/FSO transmission. The latter will be compared with QC-LDPC codes. The use of mixed RF/FSO cooperative transmission systems can improve the reliability and transmission of information in networks. The results demonstrate an improvement in the performance of the cooperative RF/FSO DF system based on QC-LDPC and SC-LDPC codes compared to RF/FSO systems without the use of codes, but also to the DF systems proposed in the existing literature.

Postquantum cryptography attracts a lot of attention from the research community recently due to the emergence threat from quantum computer toward the conventional cryptographic schemes. In view of that, NIST had initiated the standardization process in 2017. Bit flipping key encapsulation (BIKE) designed by Aragon et al. is one of the promising code-based schemes among the round-3 candidates. BIKE utilizes a quasi-cyclic medium density parity check (QC-MDPC) code and incorporates a few variants derived from the McEliece, Niederreiter, and Ouroboros schemes. In this article, we present efficient and constant time implementation of BIKEI and BIKE-III in field-programmable gate array (FPGA), which has the best area–time efficiency so far. We proposed modification to the original one-round bit flipping algorithm to achieve more area–time-efficient decoding in hardware, which achieved latency of 464.73 and $556.52~\mu \text{s}$ for BIKE-I and BIKE-III, respectively, in Virtex-7. A pipelined key encapsulation architecture is proposed to speedup the key encapsulation of BIKE-I and BIKE-III, achieving the latency of 146.47 and $153.25~\mu \text{s}$ on the same FPGA platform. Considering the Artix-7 FPGA platform, our combined key generation and encapsulation module for BIKE-I is also three more area–time efficient compared with the state-of-the-art BIKE-I implementation by Aragon et al.

Given the need to improve the efficiency of data transfer, there are requirements to ensure their reliability and quality under interference. One way to improve data transfer efficiency is to use noise-resistant codes, which include a closed-form expression of the Fibonacci code, a parity code, and a permanent weight code. The result of applying these types of coding produces interference-resistant end-to-end processing and transmission of information, which is a promising approach to improving the efficiency of telecommunications systems in today's environment. This paper reports the estimation of the error detecting code capability of the Fibonacci code in a closed-form expression, as well as its comparative characteristic with a parity code and a permanent weight code for a binary symmetrical channel without memory. To assess an error detecting capability of the Fibonacci code in a closed-form expression, the probability of Fibonacci code combinations moving to the proper, allowable, and prohibited classes has been determined. The comparative characteristic of the indivisible error-detecting codes is based on an average probability method, for the criterion of an undetectable error probability, employing the MATLAB and Python software. The method has demonstrated the simplicity, versatility, and reliability of estimation, which is close to reality. The probability of an undetectable error in the Fibonacci code in a closed-form expression is V=5×10-7; in a code with parity check, V=7.7×10-15; and in a permanent weight code, V=1.9×10-15, at p10=3×10- 9. The use of the average probability method makes it possible to effectively use indivisible codes for detecting errors in telecommunications systems

In this paper, we proposed a coding scheme based on orthogonal cyclic transpose (OCT) precoding combined with low-density parity check (LDPC) code to improve the transmission performance of 128-quadrature amplitude modulation multiband orthogonal-frequency-division-multiplexing ultrawide band over fiber (128 QAM MB-OFDM UWBoF) system. The proposed scheme could not only improve the performance of the system but also average the signal-to-noise ratio (SNR) of subcarriers and reduce the difference among subchannels in practical application. The simulation results showed that compared with the traditional scheme, the receiver performance of this scheme was improved by 2.7 dB when the LDPC-coding rate was 87.5% through 70 km standard single mode fiber (SSMF) transmission and the bit error rate (BER) was 3.8 × 10−3. Besides, the constellation distribution was more convergent and uniform.

This article introduces a novel scheme, termed coded compressed sensing, for unsourced multiple-access communication. The proposed divide-and-conquer approach leverages recent advances in compressed sensing and forward error correction to produce a novel uncoordinated access paradigm, along with a computationally efficient decoding algorithm. Within this framework, every active device partitions its data into several sub-blocks and, subsequently, adds redundancy using a systematic linear block code. Compressed sensing techniques are then employed to recover sub-blocks up to a permutation of their order, and the original messages are obtained by stitching fragments together using a tree-based algorithm. The error probability and computational complexity of this access paradigm are characterized. An optimization framework, which exploits the tradeoff between performance and computational complexity, is developed to assign parity-check bits to each sub-block. In addition, two emblematic parity bit allocation strategies are examined and their performances are analyzed in the limit as the number of active users and their corresponding payloads tend to infinity. The number of channel uses needed and the computational complexity associated with these allocation strategies are established for various scaling regimes. Numerical results demonstrate that coded compressed sensing outperforms other existing practical access strategies over a range of operational scenarios.

The belief propagation (BP) decoding of short low-density parity check codes suffers from short cycles and trapping sets. A number of perturbation schemes have been proposed to overcome the limitation. This letter presents a generalized framework for multi-round BP decoding with input perturbation and proposes an improved perturbation scheme. In particular, the impulsive perturbation which is applied to only a few symbols is proposed, along with a new space selection criterion. The proposed scheme performs better than existing schemes for short codes at lower complexity and supports a parallel implementation.

Existing secret image sharing (SIS) schemes with steganography and authentication are only suitable for uncompressed grayscale images. To make it more practical, a scheme for sharing and hiding a secret image in color palette images with authentication is proposed in this paper. Three commonly used system color palettes are considered. In sharing phase, a secret image is encoded into shared bits by polynomial based SIS. The shared bits are concealed into the color palette cover image to form the stego images. Meanwhile, the authentication parity bits are generated and embedded as well. Two embedding strategies are developed for the color palette images. In authentication and recovery phase, the integrity of each stego image is verified. Then, the secret image are reconstructed by sufficient authentic stego images. Experimental results are demonstrated to show the effectiveness and merits of the proposed scheme.

In this paper, we propose a new approach to design finite alphabet iterative decoders (FAIDs) for Low-Density Parity Check (LDPC) codes over binary symmetric channel (BSC) via recurrent quantized neural networks (RQNN). We focus on the linear FAID class and use RQNNs to optimize the message update look-up tables by jointly training their message levels and RQNN parameters. Existing neural networks for channel coding work well over Additive White Gaussian Noise Channel (AWGNC) but are inefficient over BSC due to the finite channel values of BSC fed into neural networks. We propose the bit error rate (BER) as the loss function to train the RQNNs over BSC. The low precision activations in the RQNN and quantization in the BER cause a critical issue that their gradients vanish almost everywhere, making it difficult to use classical backward propagation. We leverage straight-through estimators as surrogate gradients to tackle this issue and provide a joint training scheme. We show that the framework is flexible for various code lengths and column weights. Specifically, in high column weight case, it automatically designs low precision linear FAIDs with superior performance, lower complexity, and faster convergence than the floating-point belief propagation algorithms in waterfall region.

Power line communication (PLC) medium is a very hostile environment, this is due to the fact that severe impairments adhering this means of communication, which cannot be described as a Gaussian noise. In this paper, we propose a powerful scheme to combat the impulsive noise effect and efficiently increase the transmission bit rate. The proposed technique makes use of a new hybrid coding (HC) process and a multiple input multiple output (MIMO) based orthogonal frequency division multiplexing (OFDM), namely, HC-MIMO-OFDM. The HC is mainly constructed based on the combination of convolutional codes (CC) and quasi cyclic-low density parity check codes (QC-LDPC). The HC-MIMO-OFDM stage is then followed by an orthogonal space time block code to provide more robustness under a heavy impulsive noise environment. Furthermore, the symmetric $$\alpha $$ -stable model is applied to characterize the realistic PLC noise and consequently avoid the overestimation of the overall performance in such communication systems. The obtained results showed the increase improvement in performance of the bit-error-rate with the raise of the bit rate, when going from single input single output to MIMO. In addition, it has been illustrated that there was a gain when the MIMO was supplemented with only the CC and an additional gain when the HC is considered (i.e., combination of CC plus QC-LDPC coding).

In this paper, we propose a low-power yet area-efficient fault tolerant adder by using Berger codes. The proposed Berger code checker is designed by using the current mode multi-valued logic (CM-MVL) circuits. The proposed structure, which is more area and power efficient than state-of-the-art fault tolerant adders, is able to detect all single and multi-bit unidirectional faults. The efficiency of the proposed fault tolerant adder is evaluated by comparing its characteristics to those of two state-of-the-art fault detection schemes in adders as well as the conventional duplex and parity bit checkers in a 90 nm technology. The results reveal that the proposed 64-bit Berger code checker for adders imposes up to 6.7% and 27.2% delay and area penalties, respectively with a cost of static power dissipation. In the proposed scheme, in sub threshold regime, the power penalty is just 1%, while its area overhead is only 31%. The drawback of using this scheme in sub threshold regime is that delay time introduced to the circuit is unacceptable. So, depending on the application, we should choose one of the above-mentioned schemes.

Binary compressed sensing (BCS), in which signals of interest have binary values, finds applications in areas including fault detection and wireless sensor networks. In this article, a low-complexity VLSI architecture for BCS based on interval passing algorithm is proposed. Moreover, the algorithm is modified in order to reduce its complexity without significant loss in performance, and its corresponding VLSI architecture is proposed. Binary low-density parity check (LDPC) matrices based on finite geometry have been used as measurement matrices. The proposed VLSI architectures have been synthesized in both ASIC and field-programmable gate array (FPGA) platforms. The hardware consumption of the proposed designs is independent of sparsity values. Moreover, the proposed architectures offer high frequency of operation and low reconstruction time when compared to the state-of-the-art designs. Specifically, the 65-nm ASIC realization operates at a maximum frequency of 500 and 666.67 MHz and offer a reconstruction time of 6.3 and 4.7 ns, respectively, for a $64\times 256$ deterministic measurement matrix.

We introduce adaptive coding and modulation (ACM) to direct-detection passive optical networks (PONs) operating beyond 10 Gb/s per wavelength to allow each user to transmit at the highest possible bit rate and improve network reliability. Current fixed-rate PONs must allocate significant power margin to ensure reliable long-term operation over channels that vary over time and between users. Introducing adaptive-rate transceivers with ACM is a promising low-cost solution to increasing the overall capacity of optical access networks. The proposed ACM scheme uses two-, three-, or four-level pulse-amplitude modulation (2-, 3-, or 4-PAM) at a fixed symbol rate with direct detection and low-density parity check (LDPC) codes derived from a mother code by shortening and puncturing, decoded using fixed-initialization normalized min-sum decoding. The scheme supports received optical powers spanning a 10-dB range at bit rates of 20–54 Gb/s. In a PON with 64 users transmitting at a symbol rate of 30 Gbaud and a maximum transmission distance of 25 km, the ACM scheme demonstrates more than 3 dB improvement in overall optical power budget. For a fixed margin, ACM can increase throughput up to 60% compared to fixed-rate transmission, from 25 Gb/s to 39.7 Gb/s, or from 37.5 Gb/s to over 50 Gb/s, depending on the received optical power.

This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed design can achieve a throughput of 10.5 Gb/s for a millimeter-wave 60-GHz baseband system while satisfying the low bit error rate (BER) requirements (10−7). The proposed design reduces the wiring in the routing network by 21% and improves the area by 12% compared to the conventional min-sum (MS) and normalized MS (NMS) algorithm. Additional hardware optimizations are obtained by considering the internal message passing resolution based on the BER and signal-to-noise ratio (SNR) requirements for a practical baseband system. The power consumption is efficiently reduced by the employment of a shared address generator that exploits the degree of parallelism to reduce the switching activity on a group of memory elements. The LDPC decoder is implemented with a core area of 0.14 mm2, power consumption of 81 mW at 312.5 MHz, and the area and power efficiency of 75 Gb/s/mm2 and 10.2 pJ/bit, respectively.

The manuscript presents the construction of a diagonally structured Parity check matrix using lower and upper (LU) decomposition for regular Quasi Cyclic-Low Density Parity Check Codes (QC-LDPC) with girth 12. This diagonally structured parity check matrix reduces the sparsity characteristics of QC-LDPC codes. The regular Quasi Cyclic-LDPC code has been constructed using circulant shifting and randomization method in which uniform distribution of non-zero elements, XOR operation, and pairing of row and column has been done. A Simplified Log Domain Sum-Product Algorithm (SLDSPA) is used for the decoding of the constructed code. To reduce the CPU run time of the constructed code, a column-wise loop optimization technique is applied. The frame error rate and CPU run time is calculated for different code lengths such as code1 (816, 408), code2 (1008, 504), code3 (1032, 516), code4 (1944, 972), code5 (672, 336) and code6 (504, 252). The construction of regular QC-LDPC codes on half code rate is obtained for the weight of each row is 6 and each column is given by 3. The results showing that the constructed code is better performing in terms of Low FER (10−1 to 10−7), Low SNR (0 to 3.5 dB) and Less CPU run time in milliseconds.

MCML (MOS Current Mode Logic) based implementation producing fast response and compliment output at the same time gives an impetus to the researcher to replace Bulk CMOS. Moreover, tremendous challenges faced by bulk CMOS at channel lengths below 45 nm induces a need to strive for a technological replacement of silicon in years to come. This introduces a zest in designer's mind to look for competent and novel substances to overcome the shortcoming of existing silicon. The future technology should be capable to deliver fast response, low power operation, scalable to reduced dimensions, and strong towards process variations. Carbon nanotube based technology (CNFET) is one of the reliable and competent alternative because it has most of these desired features and similar operating principle as that of CMOS. And hence, this research article focuses on a relative evaluation of CMOS and CNFET version of 3 bit parity checker at 16-nm technology nodes. The CNFET based 3 bit parity checker is faster (9.75×), it offers improvement in power dissipation (11.93×), improvement in PDP (116.39×), improvement in EDP (1135.76×) compared to CMOS counterpart. Scaling down the device emerges with a challenge of variability, just as power, delay and area, variability also has an impact on performance of the circuit. Technology scaling has significant consequences such as wider variation. This research article also presents variability analysis, in terms of delay (tp) and power-delay product (PDP) for the proposed CNFET based MCML 3 bit Parity checker circuit. Extensive simulation using 16-nm technology node are carried out by loading two nominal copies of 'CNFET based MCML 3 bit Parity checker' (Circuit under Test) at either ends—input and output. This simulation framework supports the high level integration where stand alone operation has no application in the industry. The intent of this research is to investigate the circuit with minimal variability to propagation delay and PDP. The proposed ‘CNFET based MCML 3 bit parity checker’ exhibits improvement in delay (14.01×) and improvement in PDP (242.1×) variability as compared to CMOS counterpart. Thus, the CNFET based implementation emerges out as a robust circuit showing narrower spread in variability analysis against applied VDD.

This brief presents a VLSI architecture of a high-throughput, low-latency, and power staircase forward error correction (FEC) encoder. The designed encoder achieves low latency and memory overhead by splitting the parity generation matrix and precomputing partial parity bits for the next staircase block while generating the current staircase block. The proposed encoder is designed with a multistage pipelined architecture that enables high efficiency in terms of throughput and area. Using 65-nm CMOS technology, the synthesized encoder achieves 432 Gb/s when operating at 909 MHz, with the power consumption of 323 mW.

Recently, Kim et al. proposed a modified Dual-Ouroboros public-key encryption ($${\textsf{PKE}}$$) using Gabidulin codes to overcome the limitation of having decryption failure in the original Dual-Ouroboros using low rank parity check codes. This modified Dual-Ouroboros $${\textsf{PKE}}$$ using Gabidulin codes is proved to be IND–CPA secure, with very compact public key size of 738 bytes achieving 128-bit security level. However, they did not specify on their choice of the secret key S used in their $${\textsf{PKE}}$$. In this paper, we analyze different possible choices for S in the modified Dual-Ouroboros $${\textsf{PKE}}$$ using Gabidulin codes. More specifically, we show that if S is invertible over $${\mathbb{F}}_{q^m}$$ without any restriction, then the decryption algorithm will fail. Furthermore, we show that Kim et al.’s proposal of the modified Dual-Ouroboros $${\textsf{PKE}}$$ using Gabidulin codes has secret key S over $${\mathbb{F}}_q$$ for its decryption algorithm to be correct. Then, we proposed two attacks: key recovery attack and plaintext recovery attack on their $${\textsf{PKE}}$$ with S over $${\mathbb{F}}_q$$. We are able to recover the secret key for all the proposed parameters within 235 seconds. Moreover, we show that the public key matrix in their proposal generates a subcode of Gabidulin code. As a consequence, we can apply the Frobenius weak attack on their proposal and recover the plaintext for all the proposed paramters within 0.614 second. Finally, we give a proposal for the modified Dual-Ouroboros $${\textsf{PKE}}$$ using Gabidulin codes such that it is correct and secure, by considering certain restrictions on S over $${\mathbb{F}}_{q^m}$$.

The conventional parity-check matrix transformation algorithm (PTA) requires matrix inversion to transform matrices of maximum distance separable (MDS) codes. However, such matrix transformation is not always guaranteed for the class of non-MDS codes. Hence, the PTA fails for binary cyclic (BC) codes. To overcome this limitation, we developed a generalized parity-check matrix transformation (GPT) algorithm for binary cyclic codes. The GPT avoids the matrix inversion step of the PTA. It permutes the columns of the parity-check matrix based on the reliability information from the channel. Results show a significant bit error rate (BER) performance gain as compared to the existing PTA. It also presents a reasonable BER performance as compared to the other soft-decision (SD) decoding algorithms. In addition, the decoder functions within a practical decoding time complexity, particularly at the message passing stage.

The existing charge-based memories like DRAM and flash are reaching their scaling limits. Phase change memory (PCM) is one of the most promising emerging memory technologies due to its good scalability and low leakage power. Multi-level cell (MLC) operation in PCM, which stores two or more bits in a single cell, is necessary to achieve a high storage density. However, a reduced resistance range in multiple storage levels of MLC PCM, introduces a lot of soft errors because of the resistance drift phenomenon. The poor reliability of MLC PCM requires strong error correction codes (ECC) which could severely degrade the storage density and performance. In this paper, we propose a cost-effective reliable MLC PCM architecture for improving MLC PCM reliability, storage density and performance. The proposed architecture exploits the data-dependent nature of resistance drift problem to reduce the ECC overhead. A simple state mapping is used to generate virtual data, which is half of the actual data size. ECC parity bits are generated based on virtual data bits instead of actual message bits, thus resulting in a reduced number of cells for parity bits. This improves the reliability and storage density of MLC PCM. The performance is also improved by minimizing the ECC overhead. Simulation results show an improvement of about 104 times in reliability and 10.9% in storage density compared to a conventional MLC PCM which uses a typical error correction scheme. Performance and energy efficiency are also improved up to 13.7% and 10%, respectively, by the proposed architecture.

Since their inception in 2008, polar codes have been shown to offer near-capacity error correction performance across a wide range of block lengths and coding rates. Owing to this, polar codes have been selected to provide channel coding in the control channels of Third Generation Partnership Project (3GPP) New Radio (NR). The operation of the 3GPP NR polar codes is specified in the 3GPP standard TS 38.212, together with schemes for code block segmentation, Cyclic Redundancy Check (CRC) attachment, CRC scrambling, CRC interleaving, frozen and parity check bit insertion, sub-block interleaving, bit selection, channel interleaving and code block concatenation. The configuration of these components is different for the uplink, broadcast and downlink control channels. However, the lack of visualisations and diagrammatic explanations in TS 38.212 limits the accessibility of the standard to new readers. This motivates the aims of the paper, which provides detailed tutorials on the operation and motivation of the components of the 3GPP NR polar codes, as well as surveys of the 3GPP discussions that led to their specification. Furthermore, we comprehensively characterize the error correction and error detection performance of the 3GPP NR polar codes in the uplink, broadcast and downlink control channels.

The combination of non-orthogonal multiple access (NOMA) and multi-input multi-output (MIMO) approaches has been considered as assuring multiple access for the fifth generation technology. In this study, the performance of a 2 × 2 MIMO–NOMA system with low-density parity check (LDPC) codes is investigated. Redundancy with randomly interleaved differential encoding (R-RIDE) is proposed and applied to LDPC encoded messages by two users. LDPC decoding is done using the sum-product algorithm (SPA), which has two types of decoding methods, hard-decision and soft-decision. For hard-decision, bit-flipping decoder is used and for soft-decision, probability domain, log-domain, and simplified log-domain decoders are used. Bit error rate (BER) versus signal-to-noise ratio (SNR) in (dB) and average mutual information (AMI) in (bps/Hz) versus SNR (dB) are evaluated to compare the performance of the proposed and conventional LDPC schemes in NOMA and MIMO–NOMA systems. Simulation results show that both AMI and BER of the proposed LDPC–R-RIDE in MIMO–NOMA system greatly outperforms conventional LDPC coded schemes in NOMA and MIMO–NOMA systems. Moreover, the proposed R-RIDE-LDPC in MIMO-NOMA system outperforms the proposed scheme in the NOMA system. From the simulation results, LDPC–R-RIDE with simplified log-domain decoder has the best AMI result and BER performance compared with other decoding methods.

The paper presents a new scheme of cyclic codes suitable for the correction of burst errors. This is accomplished by the proper definition of their parity check polynomials in which the difference between orders of every two consecutive elements of the utilized polynomial is unique and in order of power of 2. In the proposed polynomials, the number of applied elements is much lower than their orders (or codes’ lengths). This leads to represent codes as a class of low-density parity check (LDPC) codes, while they do not have any 4 cycle in their Tanner graphs. Considering the properties of the circulant matrix and structure of the defined polynomials, it is proven that codes have the optimum burst error-correcting capability. This is evident for short and long length codes. Moreover, it is shown that constructed codes can be combined with Fire codes and demonstrate cyclic codes that are applicable for the simultaneous correction of random and burst errors.