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In this paper we address the Lee Voronoi diagram of polygonal objects and present applications in VLSI layout and manufacturing. We show that the Lee Voronoi diagram of polygonal objects consists of straight line segments and thus it is much simpler to compute than its Euclidean counterpart; the degree of the computation is significantly lower. Moreover, it has a natural interpretation. In applications where Euclidean precision is not essential the Lee Voronoi diagram can provide a better alternative. Using the L[sub ∞] Voronoi diagram of polygons we address the problem of calculating the critical area for shorts in a VLSI layout. The critical area computation is the main computational bottleneck in VLSI yield prediction. [ABSTRACT FROM AUTHOR]