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There are many semiconductors with nominally superior electronic properties compared to silicon. However, silicon became the material of choice for MOSFETs due to its robust native oxide. With Moore's observation as a guiding principle, the semiconductor industry has come a long way in scaling the silicon MOSFETs to smaller dimensions every generation with engineering ingenuity and technological innovation. As per the 2012 International Technology Roadmap for Semiconductors (ITRS), the MOSFET is expected to be scaled to near 6 nm gate length by 2025. However, materials, design and fabrication capabilities aside, basic physical considerations such as source to drain quantum mechanical tunneling, channel to gate tunneling, and thermionic emission over the channel barrier suggest an end to the roadmap for CMOS is on the horizon. The semiconductor industry is already aggressively looking for the next switch which can replace the silicon FET in the long term. My Ph.D. research is part of the quest for the next switch. The promises of process compatibility with existing CMOS technologies, fast carriers with high mobilities, and symmetric conduction and valence bands have led to graphene being considered as a possible alternative to silicon. This work looks at three devices based on graphene using first principles atomistic transport simulations and compact models capturing essential physics: the large-area graphene RF FET, the Bilayer pseudoSpin FET, and the double electron layer resonant tunneling transistor. The characteristics and performance of each device is explored with a combination of SPICE simulations and atomistic quasi static transport simulations. The BiSFET device was found to be a promising alternative to CMOS due to extremely low power dissipation. Finally, I have presented formalism for efficient simulation of time dependent transport in graphene for beyond quasi static performance analysis of the graphene based devices explored in this work.