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In this article, Boltzmann statistics consideration is added to the charge-deficit large-signal non-quasi-static (NQS) model. The new model eliminates the nonphysical negative drain transport (as opposed to displacement) current at large drain voltage and under fast gate voltage ( $\text {V}_{\text {gs}}$ ) turn-on. The new model agrees well with the technology computer-aided design (TCAD) simulation data for turn-on and turnoff transients and for all the drain voltage ( $\text {V}_{\text {ds}}$ ) values, small or large. In addition, the model captures the temperature dependence of channel charge partition between source charge and drain charge in agreement with TCAD simulation results, thus reconfirming the importance of including Boltzmann statistics in NQS models. The new Boltzmann-aware NQS model is implemented in Verilog-A and tested using commercial circuit simulators. It is intended for the simulation of large-signal and small-signal NQS, and high-speed analog, logic and memory circuits.

In this work, safe operating area (SOA) limit of a conventional drain extended metal oxide semiconductor (DEMOS) and a ferroelectric-based DEMOS (FDEMOS) is investigated. Through qualitative analysis of their breakdown under electrostatic discharge (ESD) stress conditions using the transmission line pulsing (TLP) method, we compare the electrical-SOA boundaries. Tradeoffs associated with SOA of FDEMOS are investigated in detail including enhanced transconductance, improved subthreshold swing (SS) (due to negative capacitance (NC) property), and reduced breakdown voltage. Under gate-grounded configuration with iso-off conditions, we found that FDEMOS shows a slight reduction in breakdown voltage while maintaining comparable power figure of merit (PFOM) to DEMOS. At ${V}_{g} =0.8$ V ( ${V}_{\text {OV}}~\sim ~0.2$ V), FDEMOS shows a 9% decrease in breakdown voltage, resulting in a substantial 57% improvement in ON-resistance and a $2\times $ increase in PFOM. However, at ${V}_{g} =1.8$ V ( ${V}_{\text {dd}}$ ), there is only a 9% improvement in ON-resistance along with a 23% degradation in breakdown voltage, which lowers the PFOM. The improvement in ON-resistance with FDEMOS significantly enhances the PFOMs for lower gate voltages. FDEMOS is found to be superior to DEMOS when operating under low gate voltages.

This article introduces a compact model for single-gate and multigate thin-film transistors (TFTs) based on the Berkeley short-channel IGFET model-common multiple gate (BSIM-CMG) framework, valid in all regions of TFT operation. We develop a model for the channel charge density, including the impact of traps in the amorphous/polycrystalline channel of TFT, based on a linear potential profile approximation along the gate-normal direction. We further develop explicit, charge-based compact models for current and terminal charges. Unlike previous models, this model implicitly includes the impact of trap-limited conduction mechanism. In addition, we include the impact of Schottky source/drain contact resistances and temperature dependencies. The model is carefully validated with published experimental data of TFTs using diverse channel materials, including oxide semiconductors (OSs) and poly-Si, and various geometries, spanning applications in displays and emerging 3-D back-end-of-line (BEOL) integration scenarios.

In this work, we present a compact temperature-dependent model for bulk MOSFETs with applicability down to the cryogenic range of temperatures and validate it against the experimental data. The long-channel and low-threshold voltage MOSFET device is characterized by multiple bias conditions and temperatures. With decreasing temperature, the characteristics exhibit a positive temperature shift in threshold voltage, an increase in the low-field carrier mobility, higher mobility degradation, and subthreshold swing (SS) saturation. Furthermore, the transconductance shows a nonmonotonic behavior with respect to temperature. The observed temperature-dependent variations in the device characteristics have been thoroughly analyzed, incorporated into the temperature-dependent parameters of the BSIM-BULK model, and validated using our characterized data and experimental data from other recent publications. The accuracy of the model and physical correctness are effectively demonstrated by carrying out the Gummel symmetry test (GST), the slope ratio (SR) test, and the tree top test. This study also analyzes the behavior of the results of the SR and tree top tests at cryogenic temperature, presenting these findings for the first time.

In this work, parameter extraction methodology for the BSIM industry standard high-voltage (HV) device compact model is presented. An extraction procedure covers entire range of operation, including weak inversion to strong inversion region, low and high drain biases, and multiple body biases with temperature effects. The extraction procedure is validated with experimental and numerical simulation data for several configurations of HV devices, including geometric variations.

Space charge modulation (SCM), that is, the increase of charge carriers in the drift region, modulates carrier concentration in the drift region, which results in conductivity modulation (also known as the expansion effect) of laterally double-diffused metal oxide semiconductor (LDMOS) transistors. In this work: 1) a compact model for conductivity modulation is presented. Since conductivity modulation also causes a change in internal node voltage ( ${d}_{i}$ ), therefore physics in the impact ionization model of drift region which accurately captures the change in node voltage is also included; 2) an improved model of impact ionization for the intrinsic region of LDMOS transistors ( ${d}_{i}$ ) is discussed and validated across a high drain voltage for different gate voltages; 3) the topology of the substrate current flow has been modified, in accordance with the device physics; and 4) finally, this work also includes the improved model of the impact ionization to capture the body bias effect in LDMOS transistors. The new model is extensively validated with the experimental and TCAD data. The research aims to enhance the industry-standard Berkeley short-channel IGFET model-bulk (BSIM-BULK) model, ensuring compatibility with SPICE simulators.

In this article, we present a novel deep learning (DL) framework that fully automates the parameter extraction process for the BSIM-CMG unified model for advanced semiconductor devices. The framework seamlessly integrates with the BSIM-CMG model, making it applicable to diverse advanced devices such as GAA nanosheets, nanowire FETs, and FinFETs. Unlike existing approach involving DL for parameter extraction, the proposed framework combines physics-driven parameter initialization and data-driven DL enhancing the computational efficiency and making it easy to implement. It leverages the BSIM-CMG model’s versatility for initial parameter estimation, the efficiency of DL algorithms for model parameter prediction, and the adaptability to various device geometries and configuration. The framework has been successfully validated with extensive numerical simulations and experimental data from 14-nm FinFET device with varying channel widths, 12-nm nanosheet, and 24-nm nanowire FET.