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Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for the physical analysis of defects on p-GaN power HEMTs that have been electrically stressed under DC surge or voltage switching stresses. The methodology includes a backside approach for sample preparation and defect localization. It is crucial to adapt the preparation process according to the position of the defect in the device structure (including metallurgy, dielectric layers, epitaxy, etc.), which depends on the type of stress applied. In our study of the reliability of the transistor under increased electrical stress in lifetime operation mode, failure analysis is used to identify the weakest areas in the design with respect to the type of stress applied. This paper presents a failure analysis consisting of techniques such as electrical characterization, photon emission microscopy and lock-in thermography for defect localization, focused ion beam slice and view, transmission electron microscopy analysis, and frontside conductive atomic force microscopy after immersion in hydrofluoric acid. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper introduces a novel differential combiner designed to effectively address parasitic capacitances of transistors used in power amplifier (PA) designs with precise compensation at a specified frequency. The combiner consists of a λ / 4 transmission line with an integrated capacitor of value 2 C O U T at its midpoint, which ensures accurate cancellation of parasitic effects. This design connects the drain pins of two transistors, which are considered identical in this configuration. By eliminating the need for complex parasitic compensation techniques, this method significantly simplifies the design process of Doherty Power Amplifiers (DPAs). Extensive simulations validate the effectiveness of this approach, highlighting its potential as a versatile and straightforward solution for next-generation communication systems. [ABSTRACT FROM AUTHOR]

The total ionizing dose effect of Mg-doped p-GaN gate stack have been investigated in this Letter on the whole gate voltage swing arranging from −1.3 to +1.5V. Additionally, two distinct kinds of mechanisms of trap effects have been extracted, which are response to in turns three phases of mechanism, voltage-controlled, coexist of voltage/current-controlled and current-controlled. It indicates that the fast traps are located at p-GaN/AlGaN interface (ET is about 0.295–0.333 eV), while the slow traps are located at AlGaN/GaN interface (ET is about 0.393–0.485 eV). They both have increasing trap density and broader range under γ-ray radiation. When the applied gate voltage rises to about 1 V, the effects of slow trap states are significantly weakened. However, the fast trap states barely change. Finally, the complete transition into current-controlled mode is observed at 1.5 V. What is more, p-GaN/AlGaN interface traps are further extracted near the gate turn-on voltage under γ-ray irradiation rather than the voltage-controlled mechanism of weak accumulation at the threshold voltage. Under the 600 krad γ-ray irradiation, the holes trap at p-GaN/AlGaN interface is identified with the trap activation energy ET at about 0.28–0.3 eV and trap density of about 4 × 1012 cm−2 eV−1. The increase in trap induces the reduction of gate current. In summary, this work can further our understanding of radiation tolerance and trapping effects of p-GaN gate high-electron mobility transistors for power switches, especially in regard to forward conduction status. [ABSTRACT FROM AUTHOR]

Active gate driving (AGD) is a promising concept for achieving high‐performance power transistor switching. This is particularly crucial for Silicon Carbide (SiC) MOSFETs since their inherently fast switching characteristics give rise to severe overshoots and oscillations which translate into increased levels of electromagnetic interference (EMI) emissions. In this paper, an AGD strategy using a single‐pulse applied during the switching transient is considered for a 1200 V 400 A SiC MOSFET module. The effect of single‐pulse timing, load current, and temperature on the switching performance is analyzed in detail. The radiated EMI reduction benefits are quantified by H‐field and E‐field probes. A conceptual closed‐loop AGD approach is presented and compared to open‐loop operation. For the transistor turn‐off case under full load current of 400 A, experimental results show that it is possible to reduce voltage overshoot by 43.3%, voltage and current oscillations by 69.7% and 52.2% respectively, and EMI by 76.6%, with a trade‐off in the switching energy by a relatively minor increase of 18.2%, compared to the conventional gate driving case. For the turn‐on case, current overshoot was reduced by 32.7%, EMI by 52%, voltage and current oscillations by 54.6% and 52.8%, respectively, with a penalty of 50.9% increase in the switching loss. [ABSTRACT FROM AUTHOR]

This work presents a comparative study of a step-down converter controlled through the algorithm MPPT Perturb and Observe (P&O) with or without a fuzzy logic controller supplied by a photovoltaic system. This study aimed at increasing the quantity of electric energy taken over from the photovoltaic systems by the load through the DC-DC convertor. To follow up the maximum power point where the transfer is performed from the photovoltaic system to the load at maximum power, the Perturb and Observe (P&O) method was used. Two programs were elaborated in MATLAB-Simulink R2018a to control the buck convertor commanded through the P&O algorithm with or without a fuzzy logic controller. The analysis of the results showed that a higher quantity of energy is transferred from the source to the receptor circuit in the case of the buck convertor controlled through the P&O algorithm with a fuzzy logic controller. The P&O algorithm was implemented on an experimental stand at the Laboratory of Electrical Machinery and Drives of the Engineering Faculty in Bacau, with the help of a program issued in the Arduino IDE programming environment. The analysis of the results showed that for an increase in the power conveyed to the receptor circuit, there will also be an increase in the filling factor of the PWM signal that controls the power transistor in the structure of the DC-DC convertor. The P&O algorithm with a fuzzy logic controller may also be implemented in the DC-DC converters in the structure of the driving systems of electric vehicles. [ABSTRACT FROM AUTHOR]

Phase-locked loop systems (PLL) are widely used in control circuits of transistor resonant voltage inverters of induction heating installations. One of disadvantages of PLL systems is low speed, which is caused by the presence of a lowpass filter. This disadvantage is absent in self-oscillating systems, when the switching moment of the transistors is determined on each of half periods. At the same time, an asymmetry of half periods is possible, which is a significant disadvantage if there is a transformer at the output of the inverter. A self-oscillating digital control system for a resonant voltage inverter and equal half periods durations of the inverter output voltage has been developed. It can work with different methods of regulating the output current and allows to provide switching modes of transistors with minimal power losses. [ABSTRACT FROM AUTHOR]

Adders and subtractors are essential to many integrated circuits (IC), including microprocessors, and micro controllers. However, using complementary metal oxide semiconductor (CMOS) and field effect transistor (FET) technology to make conventional adders and subtractors increased transistor count and power consumption. So, this effort begins with hybrid adder-subtractor designs using FinFET and graphene nano-ribbon FET(GnrFET) nano technologies. Initial development of an enhanced full adder with carry prediction (EFOCP) based on multiplexer logic with rapid carry-output selection reduced sum estimation delays. The considerable reduction in carry-output selection time led to this finding. The dynamic path auto-configurable adder (DPAA) selects high-speed and low-speed carry propagation channels using the EFOCP module. The DPAA was also used to create a two-complement based dynamic path auto-configurable subtractor (DPAS). Last, the dynamic path auto-configurable joint adder-subtractor (DPAJAS) combines DPAA and DPAS. Compared to existing approaches, the proposed DPAJAS design reduces Total Energy Consumption (TEC) by 23.3%, Total Path Delay (TPD) by 17.9%, and Carry Out Rise Delay by 18.2%. It also reduces Carry Out Fall Delay (COFD) by 19.4%, Sum Rise Delay (SRD) by 18.2%, and Sum Fall Delay by 18.3%. Finally, the proposed DPAJAS reduces Average Power Consumption (APC) 17.6%. These enhancements demonstrate the higher performance and efficiency of the proposed EFOCP, DPAA, DPAS, and DPAJAS designs. [ABSTRACT FROM AUTHOR]

The conventional planar Metal-Oxide-Semiconductor FETs (MOSFETs) are being replaced with Fin Field-Effect Transistors (FinFETs) due to their improved ability to manage power dissipation, propagation delay, leakage current, and short channel effects. Process variability is an issue for planar MOSFETs, however the amount of dopant ions in FinFETs reduces device performance variability. In this study, a Static-Random Access Memory (SRAM) cell employing FinFET technology is designed using three MOS transistors. It is composed of two NMOS plus a single PMOS transistor. One NMOS acts as access transistor while the pull-up and pull-down functions are performed by remaining NMOS and PMOS transistors, respectively. The proposed SRAM cell is simulated using H-SPICE simulator and is compared with existing SRAM cell designs in terms delay, power consumption and transistor count. Performance analysis shows that the proposed SRAM Cell overcomes the constraint and achieves full swing storage of logic values between 0 and 1. This justifies the definition of static. Implementing a single-ended SRAM cell also has the benefit of simplifying the SRAM cell architecture, which also results in a reduction in area. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) power devices are becoming central components in high voltage electronics. However, defects at interfaces and in the bulk continue to severely impact their reliability and performance. Here, we develop a charge pumping method to characterize SiC/SiO 2 interface defects in fully fabricated commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The method is then used to address spin states at the SiC/SiO 2 interface via charge pumping electrically detected magnetic resonance (CP-EDMR). We apply these methods to investigate the power MOSFET after electron irradiation over a dose range of 10 13 − 10 17 cm − 2 . We finally discuss CP-EDMR as a technique to interrogate spins during device operation for real-time monitoring of the device quality, performance, and degradation and as a probe for local magnetic fields. [ABSTRACT FROM AUTHOR]

The LM2990-integrated circuit family was among the first low-dropout voltage regulators to use a coupling diode to reduce a quiescent current. In certain conditions, the coupling diode, connected between the output terminal and the driver transistor collector contact, activates to supply the serial power transistor base current from the load. Nonetheless, an indirect characterization of the serial NPN transistor was affected, making it difficult to estimate its forward emitted current gain and a base current as a function of the absorbed total ionizing dose. The original SPICE simulation model had some limitations with generating the faithful simulation of radiation effects in samples supplied with a non-ideal voltage source. Therefore, a novel four-step computer simulation method was developed to specify bias and load conditions when the coupling diode reaction would not negatively affect the characterization of the serial power transistor. The previously reported method for estimating the serial transistor base current could be successfully used for dropout voltages that slightly exceed three equivalent diode voltage drops (that is, 2.4V) at the base-emitter junctions of the output amplifier transistors. [ABSTRACT FROM AUTHOR]

This paper proposes a new DC–DC bipolar resonance converter that combines a dual‐active‐bridge and a multi‐port resonance Buck‐Boost converter. This structure uses a resonance network between the input and output ports, which has the following advantages: it creates a constant current supply in the open‐loop mode; it keeps the current phase of the output ports constant under different loads; and it allows reversing the power from any output port by adjusting the phase shift of its switches, if the converter is connected to a DC microgrid. In this way, power can be exchanged among each of the output ports and input ports. The advantages of this converter are bidirectional power exchange, power exchange between output ports, soft switching, high efficiency, integration of transformer parasitic elements, and the modular capability to connect multiple resources at the input. Furthermore, the proposed structure of the bipolar converter has been implemented for verification purposes, and its results are presented in three modes: open loop, voltage control, and current control. Additionally, the results of different modes of power sharing and their bidirectionally are shown. [ABSTRACT FROM AUTHOR]

Copyright of Electric Machines & Control / Dianji Yu Kongzhi Xuebao is the property of Electric Machines & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

An adaptive high-efficiency light-emitting Diode (LED) backlight driver scheme has been proposed to address the issue of additional power loss caused by LED forward voltage variation. In this scheme, the peak current and the duty cycle of each LED channel are adjusted separately through an adaptive control algorithm to minimize the voltage drop on the linear current regulator (LCR) of each LED channel to reduce the excessive power loss in each LED channel and enhance the total power efficiency. A linear current regulator, suitable for adaptive control, is designed on a 0.18 μm 5V complementary metal-oxide-semiconductor (CMOS) process. Simulation results demonstrate that the linear current regulator can achieve a linearly adjustable channel current ranging from 0 to 48 mA with a current resolution of 0.2 mA. Across different process corners and temperatures, the maximum error for the full current range is less than 0.1%. The core area of chip layout is about 0.1 mm2. The complete driver prototype comprises the LCR chips, external power MOS transistors, digital module, and LED chains. The test results show that the power loss of the linear current regulator has been significantly reduced, and the power efficiency of each LED channel has been measured at around 98.1%. [ABSTRACT FROM AUTHOR]

A fast-switching low-loss field-stop insulated gate bipolar transistor with a dual control gate (DIGBT) of a semi-insulating polycrytalline silicon (SIPOS) material is proposed in this paper. Because the SIPOS has uniform high resistance, it has an approximate linear electric potential distribution. When DIGBT conducts, the higher electric potential on SIPOS causes the P-type drift region (P-drift) to generate an inversion layer of electrons, adjusting the number of carriers and making the generation of non-equilibrium carriers no longer dependent on the doping concentration in P-drift (Nd) but on the electric potential distribution on SIPOS. Therefore, it can solve the contradiction among the breakdown voltage, forward voltage drop [VCE(sat)], turn-off time (toff), and turn-off loss (Eoff) caused by the Nd. Through Technology Computer Aided Design (TCAD) simulation, the VCE(sat) of DIGBT is 30.6% lower than that of SJFS IGBT. Meanwhile, DIGBT reduces the toff by 62.8% while reducing the Eoff by 83.0% compared to SJFS IGBT. In addition, the static latch-up I–V and the forward biased safe operating area of the DIGBT have been significantly improved. This paper adjusts the number of carriers through the characteristics of SIPOS material, enabling the above-mentioned physical phenomena to be applied in insulated gate bipolar transistor power devices and achieving device performance breakthroughs. [ABSTRACT FROM AUTHOR]

Three‐phase ac choppers feature output voltage amplitude controllability and enable more compact system realizations compared to autotransformers. For the practical realization advantageously standard power transistor with unipolar voltage blocking capability such as MOSFETs can be employed as a naturally resulting offset voltage between the grid and the input‐stage starpoint ensures purely positive power transistor voltages. This offset voltage is, however, not strictly defined and may drift to higher voltage values, resulting in high power transistor voltage stresses and finally a potential overvoltage breakdown. Traditionally, the offset voltage drift is prevented by introducing discharge resistors across the input‐stage capacitors which, however, results in substantial ohmic losses. This paper analyzes the offset voltage formation in ac choppers and proposes a novel clamping modulation scheme which ensures a strictly defined and minimum time‐varying offset voltage without need for discharge resistors. Theoretical analyses and circuit simulations are finally experimentally verified with a 400 V (rms, line‐to‐line) 50 Hz grid connected three‐phase buck‐boost ac chopper with 3 kW rated power. [ABSTRACT FROM AUTHOR]

This paper presents the design of a synergistic arithmetic logic unit (SALU) that combines a complementary metal-oxide–semiconductor (CMOS) and memristors using the modified gate diffusion input (m_GDI) technique. The proposed design aims to reduce power consumption, delay, and the number of transistors, which are critical parameters in digital VLSI design. We have incorporated the m_GDI technique to implement the SALU, resulting in a lower number of transistors and reduced power consumption along with the delay and power delay product (PDP). The whole proposed architecture has been constructed using a basic m_GDI cell that consists of one p-type (pMOS) and two memristors. Combinational arithmetic circuits like full adder and full subtractor have been designed using the XOR-based m_GDI approach, and their performance will double that of current methods. A 1-to-8 de multiplexer circuit has also been utilized to perform 8 different operations for the ALU. Using Cadence Virtuoso tools in 45-nm technology, we have simulated the proposed design and evaluated its performance with existing designs. The proposed design has the potential to be a viable option for low-power and high-performance digital VLSI design applications. It delivers improved power, delay, and PDP characteristics while using fewer components. The power consumption, delay, and PDP of the proposed architecture are 9.71E−6 W, 2.141E−9 s, and 2.0789E−14 J, respectively. Furthermore, the design comprises just 33 pMOS transistors and 66 memristors, which is a lower count and unique combination in contrast to previous techniques. [ABSTRACT FROM AUTHOR]

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Real biological neurons are dynamical systems that can process a nonlinear, arbitrary input signal with a dynamic threshold voltage, exhibit refractory time, and have a smooth F–I curve. This paper presents a generalized bio-plausible neuron model with refractoriness, frequency adaptation, and dynamic threshold. The spiking characteristics of the generalized neuron are enhanced with less circuitry and fewer parameters compared to older circuits. The proposed silicon neuron can generate all known spiking behaviors, just like a biological neuron. The circuit is designed using a 180nm standard CMOS process. The entire design uses 22 transistors with a total power consumption of only 2nW for a 1nA step current at a spike frequency of 122Hz. The power consumption and spike frequency rate depend on the input current. The proposed neuron is also capable of displaying both Type I and Type II frequency response characteristics. In addition, our neuron model underwent Monte Carlo simulation with 1000 sample runs to assess its robustness and stability against process variations and uncertainties. The results indicate that the average energy consumption of the proposed neuron model falls within the range of 16pJ to 68pJ. [ABSTRACT FROM AUTHOR]

This article presents a capacitor‐less low dropout (LDO) regulator with a high power supply rejection (PSR) for system‐on‐chip (SoC) applications. With the proposed adaptive bulk‐driven feedforward (ABDFF) technique, in which the ripples are injected adaptively to the bulk of power transistor, the LDO maintains a steady PSR enhancement in wide load conditions, and a lower quiescent current and faster load transient response are realized. Post‐layout simulation results show that the proposed LDO regulator achieves −75‐dB PSR at 1 MHz from 1 to 100 mA and 60‐fs figure of merit (FoM) with a 100‐pF load capacitor. [ABSTRACT FROM AUTHOR]

GaN-based vertical superjunction high electron mobility transistors (HEMT) are recent avenues for power transistors. In this work, an enhancement mode vertical superjunction GaN-HEMT with gradient doping (GDP-SJ HEMT) is proposed and analyzed. In the GDP-SJ HEMT, the n-pillar doping concentration increases in a gradient manner from top to bottom. Whereas the concentration of the p-pillar is uniform and equivalent to the doping of the middle of the n-pillar. By optimizing the device design and doping profile, the specific-on resistance (Ron,sp) of the device has been reduced from 5.0 mΩ-cm2 to 3.79 mΩ-cm2. To the best of our knowledge, the frequency performance of vertical SJ HEMT has not been documented in the literature. As a result, we also performed a frequency study. The cut-off frequency (fT) of the proposed device is 78 MHz and the maximum frequency (fMAX) is 71 MHz. The device optimization increases the fT by 89% i.e. 148 MHz and fMAX by 67% i.e. 119 MHz. [ABSTRACT FROM AUTHOR]

Advancements in electronic technology have led to the emergence of portable devices like smartphones and smartwatches. For these devices, low-power supply management systems are crucial. In this study, the LDO (low-drop) regulator is implemented with TSMC 0.18 um CMOS high-voltage process. This chip is designed based on multi-current mirror circuits to implement a level-shifting circuit for controlling the error amplifier. The new architecture is achieved using the structure of three low-voltage operational amplifiers. The gate voltage of the power transistor is precisely driven by the level-shifting circuit, eliminating the need for a voltage limiting circuit on the power MOS's Vgs, thus enhancing the response time. This chip incorporates a temperature protection circuit that controls the feedback circuit for high-voltage MOS components. When the temperature exceeds a predefined threshold, the output shuts down immediately. Experimental results demonstrate that this chip can output voltages ranging from 3 to 19 V when the input voltage ranges from 3.5 to 20 V. The chip achieves a maximum output current of 1A and a peak conversion efficiency of 89.94%. [ABSTRACT FROM AUTHOR]

SiC devices can enhance power conversion in electric vehicles. However, traditional soldering techniques are limited by their low melting temperatures. Therefore, we used pressureless Ag sintering to assemble a 1200 V/200 A SiC metal-oxide-semiconductor field-effect transistor power module and compared the long-term reliability, electrical properties, and driving performance of the module with those of a similar module assembled using the solder Sn-3.0Ag-0.5Cu (SAC305). To assess sinter joint reliability, we performed power cycling tests over two temperature ranges, 50–150°C and 50–175°C, for 15,000 cycles. Subsequently, we compared the breakdown voltage (BVDSS) and drain-source on-resistance (RDS(ON)) of the SiC power modules and performed cross-sectional analyses of the device bonding interfaces. No difference in BVDSS was found between the Ag-sintered and SAC305-soldered joints. However, the RDS(ON) exhibited minimal variation for the Ag-sintered module but significantly varied for the SAC305-soldered module, suggesting that the former better maintained its characteristics. Furthermore, the electrical characteristics of the SAC305-soldered module underwent more significant alterations with increasing temperature change during power cycling, indicating that cracks propagated throughout the SAC305 soldered joint over time. Therefore, Ag sintering was quantitatively validated as the superior die attachment technology compared to soldering for long-term reliability. [ABSTRACT FROM AUTHOR]

Ternary circuits are promising due to their lower interconnect complexity, storage requirement, and lesser pin count than binary circuits. The adder is one of the most important building blocks of a digital processor. This paper proposes carbon nanotube field effect transistor (CNTFET)-based 'exact' and 'approximate' ternary full adders (TFA). The CNTFET is attractive for realizing multi-valued logic (MVL)/ternary circuits because its threshold voltage can be changed by altering the diameter of its carbon nanotube (CNT). The exact ternary adders are realized using unary functions and multiplexers. The circuit size of only the 'Sum' block of a TFA is pruned in approximate ternary full adders by varying degrees for achieving superior performance in terms of transistor count, delay, and power consumption compared to the 'exact' TFAs. This performance gain in approximate TFAs is obtained at the cost of accuracy in some of the 'Sum' outputs. Circuits are simulated with HSPICE using a 32 nm CNTFET technology node at various supply voltages and temperatures. The proposed exact adders exhibit lower power consumption and transistor count, higher robustness, and lower power delay product (PDP) and energy delay product (EDP) than existing ternary adders. The improvement in PDP of the proposed exact TFAs varies from 20 to 96% compared to existing TFAs. The performance of the exact TFAs is then further improved by approximating its 'Sum' block in approximate TFAs. Image blending is used to demonstrate the effectiveness of approximate ternary adders in error-tolerant applications. [ABSTRACT FROM AUTHOR]

In this paper, a new frequency domain behavior model for radio frequency (RF) power transistors based on a hyper‐parameter optimized Gaussian process regression (GPR) method is presented. The chaos game optimization (CGO) algorithm is used to optimize GPR hyperparameters, resulting in the CGO‐GPR model. The basic theory as well as the details of the modeling process are presented. Validation of the model is conducted using a 10‐watt GaN power transistor. Compared to the standard GPR model, the proposed model achieved a significant improvement. Furthermore, the comparison with the particle swarm optimization (PSO) based GPR model (PSO‐GPR) showed that the proposed model allows achieving superior performance, thereby confirming the effectiveness of the developed modeling technique. [ABSTRACT FROM AUTHOR]

Cold metals with an energy gap around the Fermi level have been shown a great potential for reducing the power dissipation of transistors and diodes. However, only a limited number of 2D cold metals have been studied. In this work, we explored 3D cold metals through a systematic material search and found 252 types in the database. We performed first-principles calculations to investigate the conductance and work functions of 30 cold metals for material selection. Additionally, we studied the thermoelectric properties of four typical cold metals, which possess much larger Seebeck coefficients and figure-of-merits than conventional metals, by one and two orders of magnitude, respectively. Specifically, we constructed a monolayer MoS2 transistor with a cold metal contact of ZrRuSb. Our quantum transport simulations indicate that cold metal contacted MoS2 FETs exhibit a subthreshold swing smaller than 60 mV decade−1 over four decades, and on-state currents over 1 mA μm−1 are achieved at a supply voltage of 0.5 V. Our research provides a theoretical foundation and material basis for exploring 3D cold metals in developing electronic and thermoelectric devices. [ABSTRACT FROM AUTHOR]

This paper introduces an innovative Magnetic Switch (MFS) designed to control and alter magnetic flux within energy system components, offering an alternative to conventional power electronic devices. The MFS comprises a low-current control coil, a control core, and a high-density magnetic flux-carrying main core combined with a main coil energy system. In this novel magnetic configuration, when a low-power current excites the control coil, the magnetic flux in the main core (supplied by the main coil) decreases to nearly zero. Conversely, when the control coil disconnects from the power source, the magnetic flux within the main core attains its maximum value. This operation positions the MFS as a groundbreaking concept within magnetic-based energy systems, akin to transistors in power electronics. The main outcomes of the MFS concept are that it can vary the magnetic flux of the main core in the large range, and it is a fast magnetic switch with a simple and low power loss control circuit and an independent control coil from the main coil. Analytical studies thoroughly elucidate the performance and advantages of this proposed magnetic switch, substantiated by Finite Element Method simulations and experimental prototype outcomes. [ABSTRACT FROM AUTHOR]

The paper describes the results of investigations illustrating the influence of the method of determining the excess of junction temperature and the selection of a function approximating the thermometric characteristic used in the procedure of measuring thermal resistance of a power MOS transistor on the measurement results. The investigations involved the measurements made using an indirect electrical method. Three methods of determining the excess of junction temperature of the transistor are presented, using a linear function and nonlinear function approximating thermometric characteristics. The thermal resistance measurement results obtained using each of the considered methods were compared. The measurement error caused by the selection of the considered methods was also analyzed. [ABSTRACT FROM AUTHOR]

A nonlinear capacitance compensation technique is presented in this paper to enhance the linearity of a power amplifier (PA) in the GaN process. The method involves placing an MSM varactor device alongside the GaN HEMT device, which works as the amplifying unit such that the overall capacitance observed at the amplifier input is constant, thus improving linearity. This approach is a reliable and straightforward way to improve PA linearity in the GaN process. The proof-of-concept prototype in this study involves the fabrication of a PA device using a standard GaN HEMT process, which successfully integrates the proposed compensation technique and demonstrates excellent compatibility with existing processes. The prototype has a saturation output power of 18 dBm, a peak power-added efficiency of 51.8%, and a small signal gain of 15.5 dB at 1 GHz. The measured AM–PM distortion at the 5 dB compression point is reduced by more than 50% compared to that of an uncompensated device. Furthermore, the results of third-order intermodulation distortion demonstrate the effectiveness of the linearity enhancement concept, with values improved by more than 5 dB in the linear region compared to those of the uncompensated device. All of the results demonstrate the potential utility of this design approach for wireless communication applications. [ABSTRACT FROM AUTHOR]

This article presents a comprehensive comparative evaluation of a three-phase Three-Level (3L) Flying Capacitor Converter (FCC) and a Stacked Polyphase Bridge Inverter (SPBI), specifically a converter system formed by two Series-Stacked Two-Level three-phase Converters (2L-SSC), for the realization of a 7.5 kW Integrated Motor Drive (IMD) with a high short-term overload capability. The 2L-SSC requires a motor with two three-phase windings and a split DC-link, but uses standard six-switch, two-level transistor configurations. In contrast, the bridge legs of the 3L-FCC feature flying capacitors whose voltages must be actively balanced. Despite the 800 V DC-link voltage, both topologies employ the same set of 650 V GaN power transistors, i.e., the same total chip area, and if operated at the same switching frequency, show identical semiconductor losses. Electric Discharge Machining (EDM) damage of the motor bearings is a relevant issue caused by the common-mode (CM) voltages of the inverter stage. The high effective switching frequency of the 3L-FCC and the possibility of CM voltage canceling in the 2L-SSC facilitate mitigation of EDM by means of CM chokes, whereby a substantially smaller CM choke with lower losses suffices for the 2L-SSC; based on exemplary designs, the 2L-SSC features only about 75% of the total volume and 85% of the nominal losses of the 3L-FCC. If, alternatively, motor-friendliness is maximized by including DC-referenced sine-wave output filters, the 3L-FCC's higher effective switching frequency and the 2L-SSC's need for two sets of filters due to the dual-winding-set motor change the outcome. In this case, the 3L-FCC features only about 60% of the volume and only about 55% of the 2L-SSC's nominal losses. [ABSTRACT FROM AUTHOR]

The switching control circuit in a DC to AC inverter is the critical part that is applied to control the power transistors insulated-gate bipolar transistor (IGBTs) and metal-oxide semiconductor field-effect transistor (MOSFETs). This paper proposes a high-performance and low-cost pulse width modulation (PWM) control signal with a 120° phase shift circuit for a twolevel three-phase inverter. Typically, a PWM signal with a 120° phase shift for three-phase inverters is generated with the help of analogue components with more complicated designs and power losses or by using a microcontroller with necessary programming or coding. The proposed solution is to design a 120° three-phase shift circuit based on D flip-flops and the 555-timer to generate the clock signal for the flip-flop input in addition to the dead-time control circuit. The proposed circuit is controlled by one square wave signal as an input signal to generate six output PWM control signals at 50 Hz to operate six MOSFETs in the three-phase inverter. Simulation results in power simulation software PSIM and PROTEUS simulation tools are used to verify the proposed circuit. Hardware implementation of the proposed circuit and three-phase inverter is carried out to validate the performance of the proposed design. [ABSTRACT FROM AUTHOR]

A novel frequency domain behavioral modeling method for gallium‐nitride (GaN) devices is presented in this article. By utilizing a multi‐dimensional polynomial function, the proposed technique interpolates DC‐bias voltage and temperature based on the Canonical section‐wise piecewise linear (CSWPL) model framework. A detailed description of the model's theory is provided. With data from 10‐W GaN devices, the model was implemented in commercial software and validated through both DC and radio frequency (RF) tests. A robust predictive ability is demonstrated by the obtained results, thus proving the accuracy of the developed modeling method. This model is superior to the standard CSWPL model in that it is capable of predicting transistor behavior at different bias voltages and temperatures using a single set of parameters, thereby greatly reducing the complexity of the model and the time required for extraction. [ABSTRACT FROM AUTHOR]

This paper presents a novel poly‐harmonic distortion (PHD) model that incorporates the DC input and output bias voltages using Gaussian process regression (GPR). Simulation tests were conducted using a 10‐W gallium nitride (GaN) HEMT transistor from Wolfspeed, and the model implementation test was performed in the Keysight Advanced Design System environment. The results showed that the GPR‐based PHD model exhibited good performance in predicting both fundamental and harmonic behaviors over a wide range of bias variations with significant advantages over basic linear regression methods. Additionally, the model accurately predicted load‐pull simulations. The measurement test was conducted using a 6‐W GaN device, and the results showed a mean error of 2.22% and 4.54% for the fundamental and second harmonic of the reflected wave, respectively. [ABSTRACT FROM AUTHOR]

This study analyzed the efficiency impact of a MOSFET output parasitic capacitance ( C o s s ) on a full-bridge LLC DC/DC converter. The core of the converter was the control chip for a half-bridge LLC DC/DC converter, and the output signal of the chip controlled the first-arm power transistors of the primary side of the converter. The coupling transformer reversed the output signal to control the primary side of the second arm of the power transistor. The full-bridge converter comprises a half-bridge control chip that converts the high-voltage DC power supply to a low-voltage DC power supply, which is then synchronously rectified and supplied to the load. The primary side of the power transistor achieves a zero-voltage switching (ZVS) state through the resonance of the LLC converter. This design gives the converter high power density and a simple structure. Furthermore, to determine the appropriate output parasitic capacitance for improving converter efficiency, this study analyzed the effect of the output parasitic capacitance on the switching loss and conduction loss of the power transistor on the basis of the output parasitic capacitance of the primary-side power transistor. A 1200 W converter prototype was fabricated in this study, and when the output was 300 W, efficiency increased from 92.603% to 93.462%, a 0.859% increase. The empirical results verified the feasibility of the proposed theory. [ABSTRACT FROM AUTHOR]

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18- μ m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25 mA in 500 ns edge-time for 140 pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response. [ABSTRACT FROM AUTHOR]

Today, the main concern of digital circuit designers is reducing the power of portable equipment due to the limitation of charging their batteries. One of the ways to reduce power consumption is to use approximate units in systems that have the ability to tolerate faults. Another solution to consider is designing circuits with Multi-Valued Logic (MVL), which can also reduce power consumption. The use of CNTFET transistors in MVL circuit designs can lead to higher efficiency in integrated circuits, particularly in terms of power, speed and area. Full adders are essential arithmetic modules in processors and serve as the cornerstone of digital systems. In this research study, we aimed to design an Approximate Ternary Full Adder (ATFA) with the minimum number of transistors and power consumption. Based on simulations conducted using Synopsys HSPICE in Stanford's 32 nm CNTFET technology, the proposed ATFA design demonstrated superior performance compared to previous similar designs, particularly in terms of average power consumption, delay, and energy consumption. In addition, according to the examination of noise immunity curves, the proposed circuit has higher pulse noise amplitude in all pulse widths than other circuits. Meanwhile, at the program level, image composition has been considered to study accuracy criteria such as peak Signal-to-Noise Ratio (PSNR), Structural Similarity (SSIM), and Figures Of Merit (FOM) in image synthesis, supported the superior performance of our proposed circuit compared to other similar circuits. [ABSTRACT FROM AUTHOR]

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency. [ABSTRACT FROM AUTHOR]

Organic electrochemical transistors (OECTs) based complementary inverters have been considered as promising candidates in electrophysiological amplification, owing to their low power consumption, and high gain. To create complementary inverters, it is important to use highly stable p‐type and n‐type polymers with well‐balanced current. In this study, the electrochemical stability of p‐type ladder‐conjugated polymer‐based OECT is improved through an annealing process that maintains its doped‐state drain current from 76% to 105% after 4,500 cycles in ambient environment. Next an OECT‐based complementary inverter made from p‐type and n‐type ladder‐conjugated polymers (PBBTL and BBL) that possess ultra‐low power consumption (≈170 nW), high gain (67 V/V), and high noise margin (92%) with full rail‐to‐rail swing, is presented. Furthermore, its potential for amplifying the envelope of surface electromyography (EMG) for robotic hand control is demonstrated. The high variation in the output (0.35 V) allows the amplified EMG signals to be directly captured by a commercial analog‐to‐digital converter, which in turn controls the robot hand to grasp different objects with low delay and low noise. These results demonstrate the capability of OECT inverter‐based amplifier in future signal processing‐free human‐machine interface, particularly useful for prosthetic control and gesture control applications. [ABSTRACT FROM AUTHOR]

This work analyzes the impact of working conditions on the current collapse (CC) phenomenon for an automotive GaN device. For this purpose, some sensing circuits have been compared to find the most suitable for the considered GaN family. Simulations of the testing schematic have been performed, a prototype board has been created, and some measurements have been taken. Finally, the work has investigated the effect on the CC of the input voltage, current level, switching frequency, and duty cycle. The key outcome is that the temperature increment mitigates the CC phenomenon, which implies that the on-state resistance worsening (dynamic/static ratio), which is due to the CC, reduces with increasing temperature. Therefore, the typical increment of the dynamic on-resistance (RDSON) with increasing temperature is ascribable to the increment of the static one with temperature, while it is not at all an exacerbation of the current collapse phenomenon. [ABSTRACT FROM AUTHOR]

The requirements and details of designing a measuring cell and low-back-action deeply-cooled amplifier for quantum measurements at 10 mK are discussed. This equipment is a part of a microwave single-photon counter based on a superconducting flux qubit. The high-electron mobility transistors (HEMTs) in the amplifier operate in unsaturated microcurrent regime and dissipate only 1 μW of dc power per transistor. Simulated amplifier gain is 15 dB at 450 MHz with a high-impedance (≈ 5 kΩ) signal source and standard 50-Ω output. [ABSTRACT FROM AUTHOR]

Ripple carry adders, however simple in design, retain precious operations that make them a necessary tool in the world of digital circuits. These adders find their place within the core of processors and Arithmetic Logic Units (ALUs), effortlessly performing essential computation operations with precision and reliability. Ripple carry adders exhibit commendable power efficiency, ensuring optimal energy utilization in digital circuits. With their streamlined design and efficient operation, these adders minimize power consumption, making them a smart choice for energy-conscious applications where every watt counts. Two cutting-edge techniques are opted to enhance the power efficiency of the ripple carry adder: Leakage Control NMOS Transistor (LCNT) and Stackly Arranged low Power ON transistor (SAPON). Less power is needed in the LCNT approach by making the route between the supply voltage (VDD) and the GND (ground) more resistive. During the changeover step, SAPON avoids leakage current from a short circuit. The power consumption is reduced in RCA circuit using low power reduction ways like LCNT, SAPON. These circuits are dissembled in the cadence tool with 45nm technology. [ABSTRACT FROM AUTHOR]

In this study, an electromagnetic actuator is presented, that features precise proportional action and wide displacement capabilities. This actuator operates in two distinct modes. In the proportional mode, the actuator positions its mobile equipment within a 0 to 14 mm range, governed by the balance between electromagnetic force and spring elastic force. By employing the pulse width modulation (PWM) principle, the electronic control section finely tunes the duty cycle factor and the coil current, thus achieving precise displacement control. The displacement control was further enhanced through the integration of a magnetic sensor that correlates movement with the Hall Voltage. This additional feature augments the actuator's precision by providing real-time feedback on the position of the mobile equipment, thereby refining the overall control mechanism. In the modulated mode, the actuator's oscillation frequency spans from 1Hz to 10 Hz, requiring control from the arbitrary signal generator. The PWM waveform controller DRV101 and the related electronic circuits are powered by two stabilized encapsulated continuous voltage sources that are compact enough to fit inside the actuator housing. The final power stage was represented by two power IGBT transistors that are powered by an external continuous voltage source. Experiments were also realized for heat management and to measure the plunger force at different distances between 0 and 14 mm. These analyses aim to optimize performance across both operational modes, advancing the efficiency and reliability of precision control systems in automated processes. [ABSTRACT FROM AUTHOR]

This review presents a concise overview of RF (radio frequency) power transistor behavior models, which is crucial for optimizing RF performance in high-frequency applications like wireless communication, radar, and satellites. The paper highlights the significance of accurate modeling in understanding transistor behavior and traces the evolution of behavior modeling techniques. Different behavior modeling strategies, such as LUT (look-up table) based models, polynomial equation-based models, and machine learning based models, are discussed along with their unique characteristics and modeling challenges. The review explores the difference between behavior models and the conventional empirical or physics-based modeling approaches, addressing the challenges of the accurate characterization of transistors at high frequencies and power levels. This paper concludes with an outlook of emerging trends, such as physical models combined with behavior models, shaping the future of RF power transistor modeling for more efficient communication systems. [ABSTRACT FROM AUTHOR]

The mechanism for the high drain-source current density, IDS≈ 1.3 A/mm, measured in a field effect transistor based on hydrogen-terminated diamond, is explained by the Mott insulator-metal transition (IMT). A local metal phase satisfying the Mott criterion for an IMT occurs in a p-type semiconductor formed by coupling between hydrogen and carbon on the surface of diamond. The local Mott metal phase on the surface of a p-type semiconductor leads to high carrier and current densities, and the transistor utilizing this effect is construed as a Mott power transistor. A channel material consisting of local Mott metal regions on the surface of a p-type semiconductor, such as hydrogen-terminated diamond, may be considered an inhomogeneous, topological Mott insulator. [ABSTRACT FROM AUTHOR]

This paper examines the features of the metallization unit of a power transistor with a vertical channel. It consists of alternating layers based on depth and includes titanium, titanium nitride and tungsten. Thick-film aluminum wiring is placed on the surface of the silicon substrate. Based on Auger spectroscopy and analysis of transmission electron diffraction patterns, it was revealed that a titanium dislicide film in the C54 phase is formed using low-temperature heat treatment and subsequent high-temperature annealing. It is shown that the introduction of special cyclic plasma treatment after deposition of a layer of titanium nitride using the metal-organic chemical vapor deposition method (MOCVD) made it possible to reduce the resistance of the films and reduce the level of mechanical stress. It has been shown that the addition of rhenium, titanium and nitrogen in the range of 5–10 at % allows you to reduce the mechanical stress of the tungsten layer by 3–5 times. Depending on the method of deposition of tungsten (magnetron or chemical), we have proposed two design options for this unit. A method for forming aluminum wiring based on thick-film aluminum using a sacrificial layer of titanium nitride is proposed. The proposed solutions provide the opportunity to improve the electrical and mechanical properties of the metallization unit of MIS transistor structures with a vertical channel. [ABSTRACT FROM AUTHOR]

The work is devoted to the study of high electron mobility transistor (HEMT) based on gallium nitride (GaN) in order to find the optimal composition and thickness of the buffer layer for the development of a power normally-off transistor with the highest possible breakdown voltage. The study was carried out using Sentaurus Device software (TCAD). The work shows the dependence of breakdown voltage on modifications made to the design. In particular, it has been established that to achieve breakdown voltages of the order of 1000 V, it is necessary to have an AlGaN buffer layer in GaN HEMT with a thickness of at least 4 µm, an aluminum mole fraction of about 5%, as well as doping with carbon or iron of the order of 1018 cm–3. Doping the AlGaN buffer layer with carbon (C) or iron (Fe) increased the potential barrier in the channel-buffer heterojunction, which led to an increase in the breakdown voltage of the HEMT. Increase the breakdown voltage to 900 V was possible by increasing concentration of C or Fe in the buffer layer from 1015 to 1017 cm–3. Breakdown voltage of the Fe-doped structure begins to exceed breakdown voltage of the C-doped structure, when impurity concentration continues to increase. The current-voltage characteristics of a С-doped transistor remain stable up to a concentration of 1019 cm–3 while the current in the conducting channel of a Fe-doped transistor decreases with increasing concentration. [ABSTRACT FROM AUTHOR]

This paper focuses on the problem of the modeling of FET power transistors made of gallium nitride offered by GaN Systems, Transphorm, and Nexperia. The considered devices have been available on the market since 2014. GaN-FETs are built as a cascade connection of a normally on gallium nitride HEMT and a normally off MOSFET made of silicon. On the manufacturer's sites, one can find models of these devices for like-SPICE tools in the text form. The main goal of this paper is to evaluate the model's accuracy by comparing calculation results obtained by the use of the considered models with the authors' measurement results and datasheet. It has been demonstrated that the GaN Systems model built on controlled sources described by a set of arbitrarily selected mathematical functions more accurately reproduces the basic characteristics of a transistor. On the other hand, the models from Transphorm and Nexperia, which are constructed based on built-in semiconductor device models, more precisely calculate the values of selected functional transistor parameters. [ABSTRACT FROM AUTHOR]

A novel 1440‐V 4H‐SiC accumulation mode MOSFET (ACCUFET) with ultra‐low specific on‐resistance and improved reverse recovery performance is proposed in this article. As for the proposed SiC ACCUFET, the channel region can be completely depleted by the P‐type heavily doped polysilicon gate to build an electron barrier and realize a normally‐off device. And a Schottky barrier diode (SBD) is integrated below the trench gates on both sides, which brings the feasibility of realizing reverse conduction function of the proposed ACCUFET. Also, the p‐shield regions under the Schottky contact metal provide a good electric field shielding effect for the gate oxide. Compared with the conventional SiC trench MOSFET, the numerical simulation results show that the specific on‐resistance (Ron,sp) of the proposed ACCUFET is reduced by more than 64%. The high‐frequency figures‐of‐merit HFOM [Ron,sp × Cgd] and HFOM [Ron,sp × Qgd] of the proposed device are improved by 53.19% and 58.74%, respectively. The reverse recovery time (trr), and reverse recovery charge (Qrr) are reduced by 23.28% and 82.73%, respectively. In addition, the results also indicate that the proposed device has a better latch‐up immunity compared with the conventional SiC trench MOSFET. The excellent device performance and the simple manufacturing process provide a good prospect for the application of the proposed device. [ABSTRACT FROM AUTHOR]

Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches' output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process. [ABSTRACT FROM AUTHOR]