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The storage systems relying on the 3D NAND Flash technology require an extensive modeling of their reliability in different working corners. This enables the deployment of system-level management routines that do not compromise the overall performance and reliability of the system itself. Dedicated parametric statistical models have been developed so far to capture the evolution of the memory reliability, although limiting the description to an average behavior rather than extreme cases that can disrupt the storage functionality. In this work, we validate the application of an extreme statistics tool, namely the Points-Over-Threshold method, to characterize the read disturb reliability of a 3D NAND Flash chip. Such technique proved that the die reliability characterized through extreme events analysis can be predicted using a low number of samples and generally holds good prediction features for distribution tail events.

This work focuses on the equivalent-circuit modeling of microwave field-effect transistors. Although the purely direct approach allows obtaining a good prediction accuracy in a straightforward way without the need of any optimization, optimization algorithms are often used to achieve an improved accuracy at the cost of a higher modeling complexity. The pros and cons of empowering the direct approach with optimization algorithms are discussed by focusing the analysis on a 1000-μm periphery gallium nitride high-electron-mobility transistor on silicon carbide substrate. The comparison between the two different approaches is performed through an extensive analysis of the frequency-dependent behavior of the small-signal characteristics.

Optical wireless networks-on-chip (OWiNoC) are considered as a possible solution to overcome the communication bottleneck due to wired interconnects in modern chip multi-processor systems. The efficient implementation of optical wireless links requires considering many different aspects, including analysis and deep understanding of the effects on the propagation of the electromagnetic field induced by the discontinuities that can be found in a realistic scenario. This letter aims at showing the impact determined by some of these discontinuities on optical links designed in Silicon-on-Insulator technology, exploiting simple point-to-point interconnections as a first example. Measurements and simulations confirm that multi-path phenomena, triggered by the multi-layer structure housing the antennas and the propagation paths, can have a serious impact on the link budget, with fading effects that may compromise the performance of the link. However, in the presented experimental results, thanks to a careful choice of the chip layer structure, received powers higher than those which could have been measured for optical links fabricated in an infinite homogeneous medium are observed, thus resulting beneficial for the connection's power budget.

This paper presents a new reliability threat that affects 3D-NAND Flash memories when a read operation is performed exiting from an idle state. In particular, a temporary large increase of the fail bits count is reported for the layers read as first after a sequence of program/verify and a idle retention phase. The phenomenon, hereafter called Temporary Read Errors (TRE), is not due to a permanent change of cell threshold voltage between the program verify and the following read operations, but to its transient instability occurring during the idle phase and the first read operations performed on a block. The experimental analysis has been performed on off-the-shelf gigabit-array products to characterize the dependence on the memory operating conditions. The TRE is found to be strongly dependent on the page read, on the read temperature and on the time delay between the first and the second read after the idle state. To emphasize its negative impact at system-level, we have evaluated the induced performance drop on Solid State Drives architectures.

3D NAND Flash is the preferred storage medium for dense mass storage applications, including Solid State Drives and multimedia cards. Improving the latency of these systems is a mandatory task to narrow the gap between computing elements, such as CPUs and GPUs, and the storage environment. To this extent, relatively time-consuming operations in the storage media, such as data programming and data erasing, need to be prioritized and be potentially suspendable by shorter operations, like data reading, in order to improve the overall system quality of service. However, such benefits are strongly dependent on the storage characteristics and on the timing of the single operations. In this work, we investigate, through an extensive characterization, the impacts of suspending the data programming operation in a 3D NAND Flash device. System-level simulations proved that such operations must be carefully characterized before exercising them on Solid State Drives to eventually understand the performance benefits introduced and to disclose all the potential shortcomings.

In this work, the increase on the filament conductivity during the 1st Reset operation, by using the incremental step pulse with verify algorithm, is investigated in HfO2-based 1T1R RRAM devices. A new approach is proposed in order to explain the increase of conductivity by highlighting the crucial roles played by both metal-oxide interfaces. The top metal-oxide interface ( HfO 2 - x / Ti x O y ) plays a role in the forming operation by creating a strong gradient of oxygen vacancies in the hafnium oxide layer. The bottom metal-oxide interface ( Ti x O y N z / HfO 2 - x ) also creates oxygen vacancies, which strengthen the conductive filament tip near to this interface at the beginning of the 1st Reset, leading to the reported conductivity increase. After the 1st Reset operation the conductive filament stabilizes at the bottom interface suppressing this behavior in the subsequent reset operations. By modifying the programming parameters and the temperature, it was confirmed a constant current increase of about 9 μA during the 1st Reset regardless the operation conditions imposed.

The reliability of non-volatile NAND flash memories is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it is essential to exploit powerful correction algorithms such as the Low Density Parity Check. However, the burdens of this approach materialize in a disk performance reduction. In this work a standard decoding approach is compared with an optimized solution exploiting hardware resources available in NAND flash chips. The simulation results on 2X, 1X and mid-1X MLC and TLC NAND flash-based Solid State Drives in terms of disk bandwidth, average latency, and Quality of Service favor the adoption of the presented solution in different host scenarios and realistic workloads. The proposed solution is particularly effective when high error correction interventions and read- or write-intensive workloads are considered.

Data randomization has been a widely adopted Flash Signal Processing technique for reducing or suppressing errors since the inception of mass storage platforms based on planar NAND Flash technology. However, the paradigm change represented by the 3D memory integration concept has complicated the randomization task due to the increased dimensions of the memory array, especially along the bitlines. In this work, we propose an easy to implement, cost effective, and fully scalable with memory dimensions, randomization scheme that guarantees optimal randomization along the wordline and the bitline dimensions. At the same time, we guarantee an upper bound on the maximum length of consecutive ones and zeros along the bitline to improve the memory reliability. Our method has been validated on commercial off-the-shelf TLC 3D NAND Flash memory with respect to the Raw Bit Error Rate metric extracted in different memory working conditions.

A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition.

In this paper, a new modeling technique is proposed for extracting small-signal lumped-element equivalent-circuit models for microwave transistors. The proposed procedure is based on using an optimization approach that is improved by targeting a quasi-static behavior as additional objective function rather than only minimizing the error between the simulated and measured scattering parameters. The validity of the developed modeling methodology is successfully demonstrated by considering a 0.25x1000 $\mu \text{m}^{2}$ gallium nitride (GaN) high-electron-mobility transistor (HEMT) as a case study.

Resistive switching memory (RRAM) is a promising technology for embedded memory and its application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix–vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations, which might cause degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slopes in the programming characteristics. We test the accuracy of a two-layer fully connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a tradeoff between the FC-NN accuracy, size, and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.

We numerically analyze the etch depth as a design parameter for the realization of integrated polarization independent directional couplers. Through finite-element-method simulations, the coupling coefficients of transverse-electric (TE) and transverse-magnetic (TM) polarizations are investigated according to different etch depth levels in the coupling section of the studied device. By optimizing etching depth, the proposed coupler can perform similarly for both polarizations in broadband. According to simulation results, the minimum difference between the TE and TM coupling coefficients can be kept less than 1% in 100 nm of the wavelength range.

In this paper the performance of wireless optical links in terms of bit-error-probability is evaluated, aiming at the assessment of optical wireless network-on-chip systems based on all-dielectric antennas. In particular, a ray tracing technique is suitably exploited to account for the channel modeling of the multi-layer optical wireless communication links, whereas the dielectric antennas is designed through a parametric analysis by FDTD simulations.

Computational storage is an emerging concept in big data scenario where the demand to process ever-growing storage workloads is outpacing traditional compute server architectures. To enable this paradigm there is a call for developing accelerators that off-load some of the management routines that are usually demanded to the smartness inside the storage. For enterprise solid-state drives (SSD) this translates into a dedicated hardware that exploits the interconnection fabric of the host with the goal of improving SSD reliability/performance. In this brief, we have developed an field-programmable gate array-based neural network accelerator for the moving read reference shift prediction in enterprise SSD. The accelerator high prediction accuracy (up to 99.5%), low latency (6.5 $\mu \text{s}$ per prediction), and low energy consumption (19.5 $\mu \text{J}$ ) opens up unprecedented usage models in the storage environment.

CMOS integrated 4kbit 1T-1R memristive devices were examined in terms of device-to-device and pulse number dependent variability for the use in neuromorphic systems. Based on the variability of polycrystalline HfO2 based Resistive Random Access Memory (RRAM)devices, reliability issues for the implementation of stochastic learning rules are investigated. The switching variability of the memristive devices is demonstrated as a function of the voltage amplitude and pulse number. We demonstrate that the switching probability of the filamentary RRAM devices can emulate analog synaptic functionality. Finally, the endurance and retention characteristics of the memristive devices are analyzed to evaluate the performance and reliability of the cells used for neuromorphic computing.

We compared two approaches to use high-frequency transistor load-pull data directly into a circuit simulator. One approach is based on Artificial Neural Networks (ANN), the other on look-up tables (LUT). We discuss some practical aspects, including implementation in the CAD environment and extrapolation capability.

Producción Científica, Recently, artificial intelligence reached impressive milestones in many machine learning tasks such as the recognition of faces, objects, and speech. These achievements have been mostly demonstrated in software running on high-performance computers, such as the graphics processing unit (GPU) or the tensor processing unit (TPU). Novel hardware with in-memory processing is however more promising in view of the reduced latency and the improved energy efficiency. In this scenario, emerging memory technologies such as phase change memory (PCM) and resistive switching memory (RRAM), have been proposed for hardware accelerators of both learning and inference tasks. In this work, a multilevel 4kbit RRAM array is used to implement a 2-layer feedforward neural network trained with the MNIST dataset. The performance of the network in the inference mode is compared with recently proposed implementations using the same image dataset demonstrating the higher energy efficiency of our hardware, thanks to low current operation and an innovative multilevel programming scheme. These results support RRAM technology for in-memory hardware accelerators of machine learning., German Research Foundation (grant FOR2093)

Achieving a reliable multi-level operation in resistive random access memory (RRAM) arrays is currently a challenging task due to several threats like the post-algorithm instability occurring after the levels placement, the limited endurance, and the poor data retention capabilities at high temperature. In this paper, we introduced a multi-level variation of the state-of-the-art incremental step pulse with verify algorithm (M-ISPVA) to improve the stability of the low resistive state levels. This algorithm introduces for the first time the proper combination of current compliance control and program/verify paradigms. The validation of the algorithm for forming and set operations has been performed on 4-kbit RRAM arrays. In addition, we assessed the endurance and the high temperature multi-level retention capabilities after the algorithm application proving a 1 k switching cycles stability and a ten years retention target with temperatures below 100 °C.

The cross-temperature effect has been identified as one of the sources that limits the 3D-TLC NAND Flash reliability and performance. The physical nature of the phenomenon lies on the temperature dependency of the threshold voltage distributions that is evidenced when the memory is read at a temperature different from the one experienced during its programming. State-of-the-art solutions for mitigating the phenomenon, both at circuit and system-level, are failing to entirely cover the issues of such reliability threat. In this work we present and validate a dedicated algorithm (cross-temperature dynamic V TH tracking or CTDVT) that goes in synergy with a system like a Solid State Drive to completely suppress the cross-temperature issue.

Graphene research, already prized, is nonetheless challenged to provide material advantages that bring about unique and novel applications rather than simply an improved substitute to existing materials. Arguably driving significant progress are new approaches to its manufacture including combination with other atoms and nanobiocomposite materials that introduce new functional properties. Functionalized graphene can interface with biomolecules to provide new health sector benefits in the form of highly sensitive biosensors that may offer continuous label-free measurement of key bioactive cell molecules, innovative nanoparticles for tissue targeted drug delivery and scaffolds for tissue engineering with previously unachievable qualities favouring tissue integration and biocompatibility. We here describe graphene functionalization methods and provide recent examples of how graphene can be used to achieve biological interactions with innovative outcomes. Above all, these laboratory focused advances each contribute to an incrementally improved understanding of how different forms of graphene and its derivatives can best be tailored to meet biological demands. Much has yet to be discovered with regard to safety profiles and improved manufacture yet considering how carefully derived rational insights might be combined with computational biology to accelerate complex performance models, prospects that graphene-based biomaterials can achieve extraordinary real-world benefits are optimistically poised.