Search

The effects of substrate and epitaxial-layer thickness on the single-event upset and single-event latchup response of integrated circuits are studied using experiments and three-dimensional device simulations. Reducing substrate thickness can be an effective method for improving single-event upset and latchup immunity, but only if devices are thinned beyond their epitaxial-layer thickness. Increases in overall single-event upset threshold linear energy transfer of more than a factor of two are predicted after thinning to a wafer thickness of 0.5 /spl mu/m. Simulations predict that the single-event latchup performance of a thinned integrated circuit will be similar to that of the same integrated circuit fabricated on an epitaxial substrate of equivalent thickness. By combining wafer thinning with backside contact formation, more significant improvements in the single-event latchup threshold can be obtained.

Large differences in charge buildup in SOI buried oxides are observed for X-ray and Co-60 irradiations of SIMOX and Unibond transistors. The Co-60 response is typically worse than the X-ray response. These results are consistent with expectations derived from previous work on the relative charge yield versus field in thick oxides. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored via experiments and simulation. The worst-case bias condition is found to be either the off-state or transmission gate configuration. Simulations of the buried oxide electric field in the various bias configurations are used to illustrate the factors that affect charge transport and trapping in the buried oxides. Hardness assurance implications are discussed.

The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

Dielectric breakdown in thin gate oxides is studied with a bias-temperature ramp technique. Research grade 6.5 nm oxides with Al gates show variable current-temperature (I-T) response with increasing electric field, consistent with a wide breakdown distribution at room temperature. Industrial grade 7.0 nm thermal and N/sub 2/O-nitrided oxides show well-behaved I-T plots, consistent with narrower breakdown distributions at room temperature. In all cases, temperature-to-breakdown decreases with increasing electric field. Charge-to-breakdown Q/sub BD/ levels at elevated temperatures exceed values observed in previous work, especially for the 7 nm nitrided oxides. No significant effect of radiation exposure on high-field oxide conduction or breakdown is observed under positive, zero, or negative radiation bias for the thermal and nitrided oxides, up to 20 Mrad (SiO/sub 2/). Detectable radiation induced leakage current is observed only for heavy-ion equivalent doses greater than 10 Mrad(SiO/sub 2/). These results suggest that the long-term reliability of high quality gate oxides may not be significantly degraded by radiation exposure at levels typical of system operation.

A pre-irradiation elevated-temperature stress is shown to have a significant impact on the radiation response of a linear bipolar circuit. Thermal cycling can lead to part-to-part variability in the radiation response of circuits packaged from the same wafer. In addition, it is demonstrated that a pre-irradiation elevated-temperature stress can significantly impact the enhanced low dose rate sensitivity (ELDRS) of the LM111 voltage comparator. Thermal stress moderates and, in some cases, eliminates ELDRS. The data are consistent with space charge models. These results suggest that there may be a connection between the mechanisms responsible for thermal-stress effects and ELDRS in linear circuits. Implications of these results for hardness assurance testing and mechanisms are discussed.

Metal-oxide-silicon capacitors fabricated in a bipolar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate acceptors following high-dose-rate irradiation at 100/spl deg/C. Acceptor neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of H/sup +/ ions in the oxide and Si layers and the availability of holes in the Si depletion region. The capacitor data were used to simulate the impact of acceptor neutralization on the current gain of an irradiated npn bipolar transistor. Neutralized accepters near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that acceptor neutralization may complicate hardness assurance test methods for linear circuits, which are based on elevated temperature irradiations.

Trapped protons and electrons in the Earth’s radiation belts and cosmic rays present significant challenges for electronics that must operate reliably in the natural space environment. Single event effects (SEE) can lead to sudden device or system failure, and total dose effects can reduce the lifetime of a space-based telecommunications system. One of the greatest sources of uncertainty in developing radiation requirements for a space system is accounting for the small but finite probability that the system will be exposed to a massive solar particle event. Once specifications are decided, standard laboratory tests are available to predict the total dose response of MOS and bipolar components in space, but SEE testing of components can be more challenging. Prospects are discussed for device modeling, and for the use of commercial electronics in space. In addition, technology trends are discussed for the radiation response of microelectronics in space.

This paper addresses key issues for the cost-effective use of COTS (Commercially available Off The Shelf) microelectronics in radiation environments that enable circuit or system designers to manage risks and ensure mission success. We review several factors and tradeoffs affecting the successful application of COTS parts including (1) hardness assurance and qualification issues; (2) system hardening techniques, and (3) life-cycle costs. The paper also describes several experimental studies that address trends in total-dose, transient, and single-event radiation hardness as COTS technology scales to smaller feature sizes. As an example, the level at which dose-rate upset occurs in Samsung SRAMs increases from 1.4/spl times/10/sup 8/ rad(Si)/s for a 256 K SRAM to 7.7/spl times/10/sup 9/ rad(Si)/s for a 4 M SRAM, indicating unintentional hardening improvements in the design or process of a commercial technology. Additional experiments were performed to quantify variations in radiation hardness for COTS parts. In one study, only small (10-15%) variations were found in the dose-rate upset and latchup thresholds for Samsung 4 M SRAMs from three different date codes. In another study, irradiations of 4 M SRAMs from Samsung, Hitachi, and Toshiba indicate large differences in total-dose radiation hardness. The paper attempts to carefully define terms and clear up misunderstandings about the definitions of "COTS" and "radiation-hardened (RH)" technology.

Radiation-induced hole and electron transport and trapping are fundamental to MOS total-dose models. Here we separate the effects of electron-hole annihilation and electron trapping on the neutralization of radiation-induced charge during switched-bias irradiation for hard and soft oxides, via combined thermally stimulated current (TSC) and capacitance-voltage measurements. We also show that present total-dose models cannot account for the thermal stability of trapped electrons near the Si/SiO/sub 2/ interface, or the inability of electrons in deep or shallow traps to contribute to TSC at positive bias following (1) room-temperature, (2) elevated-temperature, or (3) switched-bias irradiation. These results require modifications to modeling parameters and boundary conditions for hole and electron transport in SiO/sub 2/. Possible types of deep and shallow electron traps in the near-interfacial SiO/sub 2/ are discussed.

Thermally stimulated current (TSC) techniques provide information about oxide-trap charge densities and energy distributions in MOS (metal-oxide-semiconductor) capacitors exposed to ionizing radiation or high-field stress that is difficult or impossible to obtain via standard capacitance–voltage or current–voltage techniques. The precision and reproducibility of measurements through repeated irradiation/TSC cycles on a single capacitor is demonstrated with a radiation-hardened oxide, and small sample-to-sample variations are observed. A small increase in E ′ δ center density may occur in some non-radiation-hardened oxides during repeated irradiation/TSC measurement cycles. The importance of choosing an appropriate bias to obtain accurate measurements of trapped charge densities and energy distributions is emphasized. A 10 nm deposited oxide with no subsequent annealing above 400°C shows a different trapped-hole energy distribution than thermally grown oxides, but a similar distribution to thermal oxides is found for deposited oxides annealed at higher temperatures. Charge neutralization during switched-bias irradiation is found to occur both because of hole-electron annihilation and increased electron trapping in the near-interfacial SiO 2 . Limitations in applying TSC to oxides thinner than ∼5 nm are discussed.

Surface micromachined comb drive and microengine fluence thresholds and failure modes were investigated in X-ray, electron, and proton total-dose environments. Very high fluence levels were necessary to induce motion degradation or lockup for normal device biasing or operation. For the abnormal biasing of ungrounded or partially grounded dice, significantly lower fault thresholds were observed, but still in a medium or high fluence range.

Thermally stimulated current (TSC) and capacitance–voltage measurements are combined via a newly developed analysis technique to estimate positive and negative oxide-trap charge densities for metal–oxide–semiconductor (MOS) capacitors exposed to ionizing radiation or subjected to high-field stress. Significantly greater hole trapping than electron trapping is observed in 3% borosilicate glass (BSG) insulators. Two prominent TSC peaks are observed in these BSG films. A high-temperature peak near 250 °C is attributed to the Eγ′ defect, which is a trivalent Si center in SiO2 associated with an O vacancy. A lower temperature positive charge center near 100 °C in these films is likely to be impurity related. The higher temperature Eγ′ peak is also observed in 10, 17, and 98 nm thermal oxides. A much weaker secondary peak is observed near ∼60 °C in some devices, which likely is due to metastably trapped holes in the bulk of the SiO2. Negative charge densities in these thermal oxides are primarily associated wit...

The impact of ion energy on single-event upset was investigated by irradiating CMOS SRAMs with low and high-energy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 /spl mu/m and integration densities from 16 Kbit to 1 Mbit. No significant differences were observed between the low and high-energy single-event upset response. The results are consistent with simulations of heavy-ion track structures that show the central fore of the track structures are nearly identical for low and high-energy ions. Three-dimensional simulations confirm that charge collection is similar in the two cases. Standard low-energy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies down to 0.5 /spl mu/m. We discuss implications for deep submicron scaling, multiple-bit upsets, and hardness assurance.

Effects of irradiation and annealing temperature on radiation-induced charge trapping are explored for MOS transistors. Transistors were irradiated with 10-keV x rays at temperatures from -25 to 100/spl deg/C and annealed at 100/spl deg/C for times up to 3.6/spl times/10/sup 6/ s. Transistor data were analyzed for the contributions of radiation-induced charge due to oxide traps, border traps, and interface traps. Increased irradiation temperature resulted in increased interface-trap and border-trap buildup and decreased oxide-trapped charge buildup during irradiation. Interface-trap buildup immediately following irradiation for transistors irradiated at 100/spl deg/C was equivalent to the buildup of interface traps in transistors irradiated at 27/spl deg/C and annealed for one week at 100/spl deg/C (standard rebound test). For the p-channel transistors, a one-to-one correlation was observed between the increase in interface-trap charge and the decrease in oxide-trapped charge during irradiation. This may imply a link between increased interface-trap buildup and the annealing of oxide-trapped charge in these devices. The observed data can be explained in terms of increased hydrogen ion transport rates to the Si/SiO/sub 2/ interface during elevated temperature irradiations. These results have implications on hardness assurance testing and potentially may be used to reduce costs associated with rebound qualification.

Identifying aging effects that impact radiation hardness of microelectronics is becoming increasingly important as military weapon systems are kept in the stockpile for times beyond their originally intended use period. In this work, burn-in effects are used to demonstrate the potential impact of thermally-activated aging effects on integrated circuit radiation hardness. Static random access memories (SRAMs) from three different commercial technologies were irradiated with different pre-irradiation stress conditions. A reduction in the total dose functional failure level was observed for SRAMs from two of the technologies subjected to pre-irradiation elevated temperature stresses. This is the first time the burn-in effect has been shown to degrade the radiation-induced functional failure level of an IC. SRAM data also show no indication that the burn-in effect will saturate, at least for the conditions examined in this work. These data indicate that long-term aging can result in more device degradation than is accounted for by present hardness assurance test guidelines, potentially causing device and/or system failure during the aging period. While only a few technologies have been examined to date, we suspect other technologies may exhibit similar long-term aging effects. Technique for including aging effects within a hardness assurance test program is outlined.

A low-voltage, radiation-tolerant, nonvolatile field effect transistor (NVFET) memory involving proton motion in SiO/sub 2/ is illustrated in both bulk Si and silicon-on-insulator devices. We discuss a mechanism by which the protons are created in the oxide layer by a forming gas anneal. At low temperature (T

A large, delayed increase is observed in the postirradiation 1/f noise of Oki pMOS transistors prior to the onset of latent interface-trap buildup. Both effects are evidently due to similar thermally activated processes involving hydrogen. The increased noise through irradiation and anneal is found to be caused not only by the generation of defects at or near the Si/SiO/sub 2/ interface, but also by an apparent transition from buried to surface channel conduction. This is evidently triggered by the passivation of dopants in the Si by hydrogen transport during irradiation and anneal. Switched bias annealing confirms many of these effects are reversible. Three types of hydrogen transport are identified in MOS oxides: dispersive transport leading to "two-stage" interface-trap buildup, retarded transport leading to latent interface-trap buildup, and blockaded transport leading to proton confinement in SiO/sub 2/. The nature of the transport appears to correlate with O vacancy density and the temperature at which hydrogen is incorporated into the SiO/sub 2/. Implications are discussed for enhanced bipolar low dose rate response, the sensitivity of pMOS dosimeters, and protonic nonvolatile memory elements.

We find that annealing oxides in a H/sub 2/ containing ambient creates positive charge in the dielectric of Si/SiO/sub 2//Si structures. The H-induced positive oxide charge is shown to be very different from radiation-induced oxygen vacancy hole traps (E' centers) in SiO/sub 2/. We find that three factors strongly influence the ability to create H-induced positive charge: temperature, hydrogen concentration in the ambient, and the density of hydrogen cracking centers. We suggest that over-coordinated O centers are responsible for this charge. The proposed over-coordinated oxygen centers may also account for the equivocal nature of several forms of positive charge that have escaped detection by electron paramagnetic resonance, such as the fixed oxide charge that forms during the thermal oxidation of Si.

Threshold-voltage and charge-pumping measurements are combined to estimate densities of radiation induced bulk-oxide, interface, and border traps in transistors with soft 45-nm oxides. Immediately after irradiation, nearly all effects usually attributed to interface traps are actually due to border traps in these devices. During positive-bias anneal at 80/spl deg/C, the interface-trap density grows by more than a factor of 10, and the border-trap density changes by less than 30%. The increase in interface-trap density is matched by a decrease in bulk-oxide-trap charge. This raises the possibility that slowly transporting or trapped protons in the oxide may be responsible for this effect. An alternate explanation is offered by H-cracking models. Latent "interface-trap" growth in harder 27.7-nm oxides is associated with (true) interface traps, not border traps. Switched-bias annealing of the soft 45-nm oxides reveals fast and slow border traps with different annealing responses. Trivalent Si defects associated with O vacancies in SiO/sub 2/, the E/sub /spl gamma//' center and the O/sub 3-x/Si/sub x/Si/spl middot/ family, are excellent candidates for slow and fast border traps, respectively. For O/sub 3-x/Si/sub x/Si, x=0 is the E/sub s/' defect; x=3 is the D center; and x=1 or 2 have been proposed as candidates for the "P/sub b1/" defect on (100) Si. A hydrogen-related complex (e.g. OH/sup -/) may also be a border trap. The practical significance of these results is discussed for (1) bias-temperature instabilities in thin oxides, (2) effects of burn-in on MOS radiation response, and (3) enhanced bipolar gain degradation at low dose rates.

Defect centers in chemical-mechanical polished MOS oxides generated by either X-ray irradiation or high-field stress have been characterized using electron paramagnetic resonance and C-V analysis. In X-ray irradiated samples equivalent densities of both oxide trap E' and interface-trap P/sub b0/ centers were detected in unpolished and polished oxides. In addition, significantly larger (6 times) densities of P/sub b1/ centers were observed in irradiated chemical-mechanical polished oxides as opposed to unpolished oxides. This suggests that the polishing process alters the SiO/sub 2//Si interface. However, the P/sub b1/ centers detected in these samples do not respond electrically like conventional interface traps or border traps. This raises questions concerning the electrical and physical nature of P/sub b1/ centers in these oxides. The high-field stress data showed no difference in the density of defect centers induced in polished and unpolished oxides P/sub b1/ centers were not observed in either oxide following high-field stress.

An electron paramagnetic resonance, thermally stimulated current, and capacitance-voltage study has been carried out on phosphorus (PSG), boron (BSG), and boron and phosphorus (BPSG) co-doped oxide films on Si. The principal spin-active defects are the phosphorus-oxygen-bole-center (POHC) and the boron-oxygen-hole-center (BOHC), which are unpaired electrons on oxygen atoms with P or B in the near vicinity. The centers are activated by hole capture. We find that holes are trapped in the PSG, BSG, and BPSG dielectrics; however, hole trapping is most effective in the PSG and BPSG dielectrics. We find that electrons are trapped to differing extents in the doped films. The BPSG films are the most efficient in trapping electrons the PSG films are the least efficient. The electrical data can be explained by assuming that the precursor to the BOHC is negatively charged and the precursor to the POHC is electrically neutral. Last, the charge trapping properties of PSG, BSG, and BPSG dielectrics are compared and contrasted with those observed in thermally grown oxides.

Defect centers generated in vacuum-ultraviolet irradiated chemical-mechanical polished oxides have been characterized using electron paramagnetic resonance and C-V analysis. Both oxide trap E{sub {gamma}} and interface trap P{sub b0} centers were detected in unpolished and polished oxides. In addition, another interface defect center known as the P{sub b1} center was only identified in the polished oxides, suggesting that the polishing process altered the SiO{sub 2}/Si interface.

We have performed an extensive study of the effects of border traps (near-interfacial oxide traps that can communicate with the underlying Si over a wide range of time scales) on the response of metal-oxide-semiconductor (MOS) devices to ionizing radiation. Estimates of border-trap densities for several types of MOS devices are obtained by capacitance-voltage (CV) hysteresis, 1 f noise, and combined CV/thermally-stimulated-current methods. A new “dual-transistor border-trap” (DTBT) technique is described in detail which combines conventional threshold-voltage and 1-MHz charge-pumping measurements on n- and p- channel MOS transistors to estimate radiation-induced oxide-, interface-, and border-trap charge densities. Estimates of border-trap charge densities obtained via the DTBT technique agree well with trap densities inferred from other techniques. In some devices, border-trap charge densities (which can be greater than 1012 cm−2 following ionizing radiation exposure) can approach or exceed interface-trap charge densities, emphasizing the need to distinguish border-trap effects from interface-trap effects in models of MOS radiation response and long-term reliability. This appears to be especially critical for MOS devices with ultrathin (less than ∼6 nm) oxides, in which border traps and interface traps likely will be the dominant defect types. Effects of border traps on MOS scattering rates, cryogenic applications, and long-term reliability assessment are also discussed.

Transistors and ICs were irradiated with or without pre-irradiation elevated-temperature biased stresses (i.e., burn-in). These stresses lead to larger radiation-induced transistor threshold-voltage shifts and increases in IC static power supply leakage current (two orders of magnitude) in stressed ICs than for ICs not subjected to a stress. In addition, these stresses led to reduced degradation in timing parameters. The major cause of the differences is less radiation-induced interface-trap buildup for transistors subjected to an elevated-temperature biased stress. These results were observed for two distinctly different technologies and have significant implications on hardness assurance testing. One could significantly (1) overestimate degradation in timing parameters resulting in the rejection of acceptable ICs and increased system cost, or (2) underestimate the increase in static supply leakage current of ICs leading to system failure. These results suggest that radiation qualification testing must be performed on integrated circuits that have been subjected to all high-temperature biased stresses experienced in normal production flow or system use. >

We have performed capacitance-voltage (C-V) and thermally-stimulated-current (TSC) measurements on non-radiation-hard MOS capacitors simulating screen oxides of modern bipolar technologies. For O-V irradiation at /spl sim/25/spl deg/C, the net trapped-positive-charge density (N/sub ox/) inferred from midgap C-V shifts is /spl sim/25-40% greater for low-dose-rate ( 100 rad(SiO/sub 2/)/s) exposure. Device modeling shows that such a difference in screen-oxide N/sub ox/ is enough to account for the enhanced low-rate gain degradation often observed in bipolar devices, due to the /spl sim/exp(N/sub ox//sup 2/) dependence of the excess base current. At the higher rates, TSC measurements reveal a /spl sim/10% decrease in trapped-hole density over low rates. Also, at high rates, up to /spl sim/2.5-times as many trapped holes are compensated by electrons in border traps than at low rates for these devices and irradiation conditions. Both the reduction in trapped-hole density and increased charge compensation reduce the high-rate midgap shift. A physical model is developed which suggests that both effects are caused by time-dependent space charge in the bulk of these soft oxides associated with slowly transporting and/or metastably trapped holes (e.g. in E/sub /spl delta//' centers). On the basis of this model, bipolar transistors and screen-oxide capacitors were irradiated at 60/spl deg/C at 200 rad(SiO/sub 2/)/s in a successful effort to match low-rate damage. These surprising results provide insight into enhanced low-rate bipolar gain degradation and suggest potentially promising new approaches to bipolar and BiCMOS hardness assurance for space applications. >

The radiation hardness of commercial floating gate 256 K E/sup 2/PROMs from a single diffusion lot was observed to vary between 5 to 25 krad(Si) when irradiated at a low dose rate of 64 mrad(Si)/s. Additional variations in EEPROM hardness were found to depend on bias condition and failure mode (i.e., inability to read or write the memory), as well as the foundry at which the part was manufactured. This variability is related to system requirements, and it is shown that hardness level and variability affect the allowable mode of operation for EEPROMs in space applications. The radiation hardness of commercial 1-Mbit CMOS SRAMs from Micron, Hitachi, and Sony irradiated at 147 rad(Si)/s was approximately 12, 13, and 19 krad(Si), respectively. These failure levels appear to be related to increases in leakage current during irradiation. Hardness of SRAMs from each manufacturer varied by less than 20%, but differences between manufacturers are significant. The qualified manufacturer's list approach to radiation hardness assurance is suggested as a way to reduce variability and to improve the hardness level of commercial technologies. >

In this paper, three-dimensional numerical simulation is used to explore the basic charge-collection mechanisms in silicon n/sup +//p diodes. For diodes on lightly-doped substrates ( >

We show that enhanced hole-, electron-, interface-, and border-trap generation in irradiated Si/SiO/sub 2//Si systems that have received a high-temperature anneal during device fabrication is related either directly, or indirectly, to the presence of anneal-created oxygen vacancies. The high-temperature anneal results are shown to be relevant to understanding defect creation in zone-melt-recrystallized silicon on insulator materials. We observe the electron paramagnetic resonance (EPR) of trap-assisted hole transfer between two different oxygen vacancy-type defects (E'/sub /spl delta///spl rarr/3 E'/sub /spl gamma// precursor) in hole injected thermal SiO/sub 2/ films. Upon annealing the hole injected Si/SiO/sub 2/ structures at room temperature, the E'/sub /spl delta// center transfers its hole to a previously neutral oxygen vacancy (O/sub 3//spl equiv/Si-Si/spl equiv/O/sub 3/) site forming an E'/sub /spl gamma// center. This process, also monitored electrically, shows a concomitant increase in the border-trap density that mimics the growth kinetics of the transfer-activated E'/sub /spl gamma// centers. This suggests that both effects are correlated and that some of the transfer-created E'/sub /spl gamma// centers are the entities responsible for the border traps in these devices. One implication of these results is that delayed defect growth processes can occur via slow trap-assisted hole motion in SiO/sub 2/. >

This paper demonstrates use of the Qualified Manufacturers List (QML) methodology to qualify commercial and military microelectronics for use in space applications. QML "builds in" the hardness of the product through statistical process control (SPC) of technology parameters relevant to the radiation response, test structure to integrated circuit (IC) correlations, and techniques for extrapolating laboratory test results to low-dose-rate space scenarios. Each of these elements is demonstrated and shown to be a cost-effective alternative to expensive end-of-line IC testing. Several examples of test structure-to-IC correlations are provided and recent work on complications arising from transistor scaling and geometry is discussed. The use of a 10-keV X-ray wafer-level test system to support SPC and establish "process capability" is illustrated and a comparison of 10-keV X-ray and Co/sup 60/ gamma irradiations is provided for a wide range of CMOS technologies. The X-ray tester is shown to be cost-effective and its use in lot acceptance/qualification is recommended. Finally, a comparison is provided between MIL-STD-883, Test Method 1019.4, which governs the testing of packaged semiconductor microcircuits in the DoD, and ESA/SCC Basic Specification No. 22900, Europe's Total Dose Steady-State Irradiation Test Method. Test Method 1019.4 focuses on conservative estimates of MOS hardness for space and tactical applications, while Basic Specification 22900 focuses on improved simulation of low-dose-rate space environments. >

Radiation-hardened technology for space applications will be evaluated in light of its survivability in the total-dose, cosmic-ray, and solar flare environments normally encountered in space. Several examples of technology development programs will be summarized, including Sandia programs over the last two decades. Techniques for optimizing the radiation hardnes of CMOS technologies for space will be discussed. For total-dose hardness, these techniques provide information about the number of radiation-induced defects and their microscopic nature, and are used to identify manufacturing processes that play an important role in the fabrication of radiation-hardened integrated circuits (ICs). For examples, the roles of high-temperature anneals, hydrogen and interfacial strain in the buildup of radiation-induced defects have received a great deal of attention, and many CMOS process flows have been designed to minimize hydrogen incorporation and reduce interfacial stress. Techniques for ensuring the tolerance of ICs to single-event phenomena (SEP) will be addressed, including the manufacture and control of high-resistivity polysilicon feedback resistors. Finally, some future trends in hardness assurance and testing that support more cost-effective qualification of ICs used in space will be covered. For total-dose, trends include wafer-level testing and X-ray irradiations; while for EP, trends include Cf-252 and laser testing

Time-dependent charge buildup and annealing processes cause the ionizing radiation response of CMOS devices and circuits to depend strongly on the dose rate of the exposure. Oxide-trap charge annealing and interface-trap buildup in nMOS transistor can lead to positive threshold voltage shifts in a space environment, while negative threshold voltage shifts are commonly observed after irradiations at typical laboratory dose rates [50–300 rad(Si)/s]. Thus, devices that pass laboratory testing can fail at the low dose rates encountered in space due to positive nMOS transistor threshold-voltage shifts above preirradiation values, i.e. “rebound”. We summarize how this issue can be addressed in total-dose hardness assurance test methods for space. An example of such a guideline is the revised U.S. military-standard ionizing-radiation-effects test method (MIL-STD 883D, Test Method 1019.4).

Electron paramagnetic resonance (EPR) and capacitance-voltage measurements have been combined to identify the chemical nature and charge state of defects in BESOI (bonded and etchback silicon-on-insulator) and SIMOX (separation by implantation of oxygen) materials. The four types of defect centers observed, charged oxygen vacancies, delocalized hole centers, amorphous-Si centers, and oxygen-related donors, are strikingly similar. In the BESOI materials, the radiation-induced EPR centers are located at or near the bonded interface. Therefore, the bonded interface is a potential hole trap site and may lead to radiation-induced back-channel leakage. In SIMOX materials, it is found that all of the defects in the buried oxide are due to excess Si. The results using poly-Si/thermal oxide/Si structures strongly suggest that it is the postimplantation, high-temperature anneal processing step in SIMOX that leads to their existence. The anneal leads to the out-diffusion of oxygen from the buried oxide, creating excess-Si related defects in the oxide and O-related donors in the underlying Si substrates. A relatively new class of defects in SiO/sub 2/, delocalized spin centers, are found to be hole traps in both SIMOX and BESOI materials. >

Charge-pumping, dual-transistor, and midgap estimates of radiation-induced interface-trap density are compared for a large number of transistors fabricated using a wide range of processing technologies. Comparisons are shown for single-transistor midgap and charge-pumping measurements and dual-transistor-mobility measurements. When conventional analysis methods are used to determine threshold voltages, there can be as much as a factor-of-two-difference in the density of interface traps measured by charge pumping and the dual-transistor-mobility and midgap techniques. Using the voltage that corresponds to twice the bulk potential as the threshold voltage, better agreement between the three techniques is obtained. In addition, the authors present a technique that combines n- and p-channel transistor charge-pumping and threshold-voltage measurements to accurately determine the threshold-voltage shifts due to interface-and oxide-trap charge. Called the dual-transistor charge-pumping technique, it contains no adjustable parameters and includes a physically based self-consistency check. >

We have identified several features of the 1/f noise and radiation response of metal‐oxide‐semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, ‘‘oxide traps’’ are simply defects in the SiO2 layer of the MOS structure, and ‘‘interface traps’’ are defects at the Si/SiO2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, ‘‘fixed states’’ are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but ‘‘switching states’’ can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface tr...

An analytical model with no free parameters has been developed which accurately describes thermally-stimulated-current (TSC) measurements spanning more than a factor of 50 in average heating rate. The model incorporates Schottky electric-field-induced barrier lowering and a temperature-dependent 'attempt-to-escape frequency' equal to approximately 10/sup 14/ Hz at 300 degrees C. Applying this model to TSC measurements provides significantly improved estimates of the energy distribution of trapped holes in irradiated SiO/sub 2/. All devices examined, including soft and (wet and dry) hard oxides from five process technologies, show similar energy distributions, with a minor peak at approximately 1.2 eV and a broad major peak centered approximately 1.7-2.0 eV above the SiO/sub 2/ valance band. It is found that the trapped-electron density in irradiated SiO/sub 2/ is proportional to the trapped-hole density over a wide range of irradiation conditions. >

An improved charge separation technique for metal-oxide-silicon (MOS) capacitors is presented which accounts for the deactivation of substrate dopants by hydrogen at elevated irradiation temperatures or small irradiation biases. Using high-frequency capacitance-voltage (C-V) measurements, radiation-induced inversion voltage shifts are separated into components due to oxide trapped charge, interface traps and deactivated dopants, where the latter is computed from a reduction in Si capacitance. In the limit of no radiation-induced dopant deactivation, this approach reduces to the standard midgap charge separation technique used widely for the analysis of room-temperature irradiations. The technique is demonstrated on a p-type MOS capacitor irradiated with {sup 60}Co {gamma}-rays at 100 C and zero bias, where the dopant deactivation is significant.

The electric-field dependence of thermally stimulated current (TSC) in irradiated MOS capacitors for TSC fields ranging from -3 MV/cm to +2 MV/cm was studied. TSC measurements at negative bias following positive-bias irradiation provide useful estimates of the net oxide-trap charge, Delta G/sub ot/, if the TSC bias is large enough to overcome trapped-hole space-charge effects. Very little TSC is observed for positive-bias irradiation. Under proper TSC bias conditions, TSC and C-V estimates of Delta G/sub ot/ agree well for thick, soft oxides, but differ significantly for thin, hard oxides. Differences between TSC and C-V estimates of Delta G/sub ot/ for thin, hard oxides are attributed to electron injection into the oxide and capture at trap sites associated with the radiation-induced trapped holes. It is shown that TSC measurements can provide insight into the location of hole traps in MOS oxides that cannot be obtained from standard C-V tests. >

The authors present a method to conservatively estimate MOS hardness in space that shares the same technical basis as MIL-STD 883C, Test Method 1019.4, but permits greater latitude in part selection for low-dose space systems. Cobalt-60 irradiation at 50-300 rad(Si)/s followed by 25 degrees C anneal is shown to provide an effective test of oxide-charge related failures at low dose rates that is considerably less conservative than Method 1019.4. For MOS devices with gate oxides thinner than 100 nm, it is shown that an elevated temperature rebound test generally is not required for systems with total dose requirements less than 5 krad(Si). For thicker gate oxides and/or higher-dose system requirements, rebound testing per Method 1019.4 generally is required to ensure that devices do not fail in space due to interface-trap effects. >

To implement the qualified manufacturers list (QML) approach to hardness assurance in a practical and cost-effective manner, one must identify technology parameters that affect radiation hardness and bring them under statistical process control. To aid this effort, the authors have developed a wafer-level test system to map test-structure and IC response across a wafer. This system permits current-voltage and charge-pumping measurements on transistors, and high-frequency capacitance-voltage measurements on capacitors. For frequencies up to 50 MHz, the system provides a complete menu of functional and parametric IC tests. Wafer maps and histograms of test-structure and IC response are presented for a 1.2- mu m radiation-hardened CMOS technology to illustrate the capabilities of the wafer-level test system. Statistical and deterministic approaches to correlate test structure and IC response are discussed for this technology. >

Thermally stimulated current and capacitance voltage methods are used to investigate the thermal stability of trapped electrons associated with radiation-induced trapped positive charge in metal-oxide-semiconductor capacitors. The density of deeply trapped electrons in radiation-hardened 45 nm oxides exceeds that of shallow electrons by a factor of {approximately}3 after radiation exposure, and by up to a factor of 10 or more during biased annealing. Shallow electron traps anneal faster than deep traps, and seem to be at least qualitatively consistent with the model of Lelis et al. Deeper traps maybe part of a fundamentally distinct dipole complex, and/or have shifted energy levels that inhibit charge exchange with the Si.

The US government has proposed a qualified manufacturers list (QML) methodology to qualify integrated circuits for high reliability and radiation hardness. An approach to implementing QML for single-event upset (SEU) immunity on 16k SRAMs that involves relating values of feedback resistance to system error rates is demonstrated. It is seen that the process capability indices, C/sub p/ and C/sub pk/, for the manufacture of 400-k Omega feedback resistors required to provide SEU tolerance do not conform to 6 sigma quality standards. For total-dose, interface trap charge, Delta V/sub it/, shifts measured on transistors are correlated with circuit response in the space environment. Statistical process control (SPC) is illustrated for Delta V/sub it/, and violations of SPC rules are interpreted in terms of continuous improvement. Design validation for SEU and quality conformance inspections for total-dose are identified as major obstacles to cost-effective QML implementation. Techniques and tools that will help QML provide real cost savings are identified as physical models, 3-D device-plus-circuit codes, and improved design simulators. >

A novel semiempirical model of radiation-induced charge neutralization is presented. This model is combined with 12 heuristic guidelines derived from studies of oxide- and interface-trap charge ( Delta V/sub ot/ and Delta V/sub it/) buildup and annealing to develop a method to predict MOS switched-bias response from steady-state irradiations, with no free parameters. For n-channel MOS devices, predictions of Delta V/sub ot/, Delta V/sub it/, and mobility degradation differ from experimental values through irradiation by less than 30% in all cases considered. This is demonstrated for gate oxides with widely varying Delta V/sub ot/ and Delta V/sub it/ and for parasitic field oxides. Preliminary results suggest that n-channel MOS Delta V/sub ot/ annealing and Delta V/sub it/ buildup following switched-bias irradiation and through switched-bias annealing also may be predicted with less than 30% error. The p-channel MOS response at high frequencies (>1 kHz) is more difficult to predict. >

The chemical kinetics of mobile-proton reactions in the SiO2 film of Si/SiO2/Si structures were analyzed as a function of forming-gas anneal parameters in the 300–600 °C temperature range. Our data show that the initial buildup of mobile protons is limited by the rate of lateral hydrogen diffusion into the SiO2 films. The final density of mobile protons is determined by the cooling rate which terminates the annealing process and, in the case of subsequent anneals, by the temperature of the final anneal. To explain the observations, we propose a dynamical equilibrium model which assumes a reversible interfacial reaction with a temperature-dependent balance.

The silicon/silicon-dioxide system provides the cornerstone of integrated-circuit technology1. Since the introduction of devices based on this system, the (largely deleterious) effects on device operation of mobile and trapped charges in the oxide layer have been studied in great detail. Contamination by alkali ions, for example, was a major concern in the early days of metal-oxide-semiconductor device fabrication2. But not all SiO2 impurities are undesirable: the addition of hydrogen, for example, has the beneficial property of rendering charge traps inactive1. Here we show that mobile H+ ions introduced by annealing into the buried oxide layer of Si/SiO2/Si structures, rather than being detrimental, can form the basis of a non-volatile memory device. These mobile protons are confined to the oxide layer, and their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Memory devices based on this effect are expected to be competitive with current state-of-the-art Si-based memories, with the additional advantage of simplicity—only a few standard processing steps are required.

The Westinghouse SA3823 64K E/sup 2/PROM radiation-hardened SONOS non-volatile memory exhibited a single-event-upset (SEU) threshold in the read mode of 60 MeV-cm/sup 2//mg and 40 MeV-cm/sup 2//mg for data latch errors. The minimum threshold for address latch errors was 35 MeV-cm/sup 2//mg. Hard errors were observed with Kr at V/sub P/= 8.5 V and with Xe at programming voltages (V/sub P/) as low as 7.5 V. No hard errors were observed with Cu at any angle up to V/sub P/=11 V. The system specification of no hard errors for Ar ions or lighter was exceeded. No single-event latchup (SEL) was observed in these devices for the conditions examined. The Analog Devices AD7876 12-bit analog-to-digital converter (ADC) had an upset threshold of 2 MeV-cm/sup 2//mg for all values of input voltage (V/sub in/), while the worst-case saturation cross section of /spl sim/2/spl times/10/sup -3/ cm/sup 2/ as measured with V/sub in/=4.49 V. No latchup was observed. The Intel 82C527 serial communications controller exhibited a minimum threshold for upset of 2 MeV-cm/sup 2//mg and a saturation cross section of about 5/spl times/10/sup -4/ cm/sup 2/. For latchup the minimum threshold was measured at 17 MeV-cm/sup 2//mg, and cross section saturated at about 3/spl times/10/sup -4/ cm/sup 2/. Error rates for the expected applications are presented.

H‐induced positive charging is observed at both the top Si/SiO2 and bottom SiO2/Si interfaces in Si/SiO2/Si structures. The response of the H‐induced positive charge to thermal annealing and electron injection is very different from that of simple oxygen vacancy hole traps in SiO2. To explain this H‐induced positive charging, we propose a scheme in which H reacts to form positively charged over‐coordinated oxygen centers in close proximity to both top and bottom interfaces. The annealing‐induced entity may also provide a natural explanation for the origin of the fixed oxide charge that forms during oxidation of Si.

Trivalent silicon Pb0 and Pb1 defects were identified at both the top Si(100)/buried‐SiO2 and buried‐SiO2/bottom‐Si(100) interfaces in high‐temperature (1320 °C) annealed Si/SiO2/Si struc‐ tures. The paramagnetic defects are generated by annealing in a flow of pure nitrogen (N2) or forming gas [N2H2; 95:5 (by volume)] at 550 °C. In addition, the forming‐gas anneal also generated positive charge in the buried oxides; significant lateral nonuniformities in the buried oxide charge density were observed following this anneal. These macroscopic inhomogeneities may be linked to previous reports of homogeneity related problems involving the SIMOX buried oxide, such as early breakdown and etch pits, suggesting that these types of measurements may be useful as nondestructive screens of SIMOX wafer quality.

An electron paramagnetic resonance study has been carried out on B‐ and P‐doped oxide films on Si. The principal defects are the boron‐oxygen‐hole‐center (BOHC) and phosphorus‐ oxygen‐hole‐center (POHC), which are unpaired electrons on oxygen atoms with B or P in the near vicinity. Our results demonstrate that the centers are activated by hole capture. We find that holes are trapped very efficiently in both B‐ and P‐doped dielectrics; however, electrons are more efficiently trapped in the B‐doped dielectrics. We find that the electrical data can be explained by assuming that the precursor to the BOHC is negatively charged and the precursor to the POHC is electrically neutral.

Evidence is provided to show that enhanced hole‐, interface‐, and border‐trap generation in irradiated high‐temperature annealed Si/SiO2/Si systems are all related either directly, or indirectly, to the presence of oxygen vacancies. We find that the calculated oxygen vacancy due to high‐temperature anneals from 800 to 950 °C in metal‐oxide‐semiconductor capacitors closely matches the radiation‐induced oxide‐trapped charge. This strongly suggests that oxygen vacancies (or vacancy‐related complexes) are the dominant hole trapping sites in this particular case. Along with the increase in radiation‐induced oxide‐trap charge, we observe a concomitant increase in the interface‐ and border‐trap densities. This suggests that in devices that receive high‐temperature anneals, all these phenomena are linked to the existence of oxygen vacancies either directly, or indirectly, perhaps via hole trapping at these vacancies.

Using electron paramagnetic resonance we have been able to identify a new oxygen‐related donor defect in the Si substrate of bonded and etchback silicon‐on‐insulator structures. This axially symmetric donor is preferentially aligned along the [100] direction, and resides close to the Si/SiO2 interface. It is tentatively suggested that the donors result from the nonoxidizing anneal received by the wafers during the bonding process.