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Container technology plays an important role in the virtualization landscape today. A container uses its own file system consisting of a stack of layers, which are stored on the execution server's disk. Containers running on the same server share the layers they have in common, and this sharing results in valuable savings in server storage space. Many containers can run on a single server, but when their resource demands grow enough, they are distributed across a cluster of nodes/servers by orchestration systems, such as Kubernetes. In this work, we found that for the same amount of containers to run, the storage required is higher for clusters consisting of a larger number of nodes. The severity of this storage overhead depends on the scheduling policy used to select the nodes that run the containers. By comparing different storage-saving scheduling policies that differ from each other in the depth of storage knowledge they leverage to make decisions, our analysis reveals that only deep, layer-level knowledge can effectively counter the growth in storage demand as the cluster size increases. Policies with coarser-grained knowledge achieve limited benefit because they achieve performance that is nearly equal to that of a random, zero-knowledge policy.

The rapid growth of storage overhead on public blockchains has urged the use of light clients that only store a small fraction of blockchain data and rely on other bootstrapped full nodes for data retrievals. Unfortunately, current blockchain light client designs are far from satisfactory. Firstly, outsourcing retrieval requests could raise severe concerns about result correctness and privacy threats. Secondly, current light clients do not support rich query and enforce fee payments to full nodes. Given that blockchain storage increases day by day, enabling effective rich blockchain queries and fairly compensating full nodes ever growing costs has become extremely necessary. In this paper, we propose a general and secure paid query framework to simultaneously meet those demands above. Specifically, we leverage the integration of trusted hardware (e.g., Intel SGX) and smart contract as a starting point for building efficient yet secure query processing with fair payments. Then, we further craft several crucial performance and security refinement designs to boost query efficiency and enforce result correctness, and also explore an enclave-facilitated fair settlement mechanism for on-chain cost optimizations. We implement a prototype of our paid query framework and the experimental result has demonstrated its practically affordable cost.

Superconductive Rapid Single Flux Quantum (RSFQ) is an emerging cryogenic technology promising a significant boost in performance and ultra-low power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS — single flux Quantum Clock Tree Synthesis — is presented. QuCTS utilizes a two stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1,049 clock sinks in 53 minutes while satisfying the clock arrival time.

As a promising alternative solution to cloud storage, decentralized storage networks (DSN) are widely anticipated to develop continuously and reshape the storage market share in the foreseeable future. In particular, one of the most important research problems is how to enforce the quality of service (QoS) in the context of storage solutions. Despite plenty of auditing-related works in the context of cloud storage, none of them can be directly applied to the decentralized storage paradigm. The challenges of designing a feasible storage auditing framework emanate from two aspects: 1) security problems unique to the decentralized settings; 2) performance overhead due to on-chain operations. In this work, we first put forward a basic storage auditing framework that satisfies the security and efficiency requirements, and outperforms the existing approaches. We also identify a critical and overlooked security problem that would compromise the integrity of storage auditing solutions in the blockchain paradigm. With our refined storage auditing design based on customized zero knowledge protocols, we propose a convenient mitigation solution in our revised security model. The evaluation results confirm that our solution would only incur a 10%-15% increase in the overall auditing costs for common usage scenarios, compared to the basic design.

Browser extensions are widely used nowadays to customize users' browsers with more functionalities, meanwhile introduce potential risks due to escalated privileges. Existing security mechanisms, such as Same Origin Policy and Content Security Policy, do not apply to browser extensions that can read and write on web applications at any time. In spite of the state-of-art industrial efforts that rely on centralized management to inspect and detect malicious behaviors massively, the detection-based method cannot analyze fast-evolving behaviors of malicious browser extensions. To this end, we adopt a novel approach to protect users from malicious browser extensions, where we consider the problem of malicious extensions on the side of web applications. From a high level point of view, web developers are allowed to specify sensitive parts in a web application by using our provided software enclave. With our proposed WebEnclave extension installed, when users visit a web application, sensitive information required for the web application to work normally is sealed into an isolated world locally that malicious extensions cannot access. Extensive evaluation of our built prototype shows it can effectively protect user secrets from malicious extensions with negligible performance overhead and usability inconvenience. We also publish source codes for public use.

Since spiking neural networks can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale spiking neural networks requires a simple and versatile silicon neuron model framework. In this paper, a spiking neuron circuit as the core device of spiking neural networks is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas-Niebur mathematical model is adopted. The improved Mihalas-Niebur model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.

Toughened glass insulators installed in overhead lines play a key role in maintaining the reliability and safety of power systems. The singular properties of toughened glass make this material particularly suitable for this application on account of its excellent dielectric properties, high mechanical strength and easiness of inspection. If the glass was damaged, it would shatter completely leaving the remaining part of the insulator, called stub, still providing mechanical connection and being easily detectable from the ground by a visual inspection. In this paper, the mechanical reliability of toughened glass insulators is investigated through the analyses of experimental data obtained from laboratory tests. First, the mechanical strength of the toughened glass in insulators and the relationship between its failing load and the geometry of the insulator are investigated by means of a novel analytical approach. Afterwards, the risk of mechanical failure of glass insulators and stubs, with the shell broken off, is analysed. The results show the mechanical reliability of glass insulators for different string configurations and for large and complex systems deployed in 220 kV and 400 kV transmission lines. Finally, the effect of the shattering rate on the reliability is studied under the most adverse conditions.

Blockchain-based Internet of Things (BC-IoT) brings the advantages of blockchain into traditional IoT systems. In BC-IoT, the smart contract has been widely used for automatic, trusted and decentralized applications. Smart contracts require frequently adjust and fast update due to various reasons such as inevitable code bugs, changes of applications or security requirements. However, previous smart contract architecture and updating mechanism are low speed and cause high overhead, because they are based on recompilation and redeployment in BC-IoT. Meanwhile, smart contract execution is so timeconsuming due to contract instruction dispatching and operand loading in the stack-based Ethereum Virtual Machine (EVM). To address these issues, we propose a new smart contract architecture and optimization mechanism for blockchain-based Internet of Things, ATOM, which provides architectural supports to update contract economically and fast executing in instructionwise for the first time, to the best of our knowledge. We design a compact Application-oriented Instruction (AoI) set to describe application operations. We can construct the bytecode of smart contract from application by directly assembling templates prebuilt upon the AoIs rather than by compilation. We also present an optimized mechanism for AoI execution to enable access addressable storage place rather than the indirect access through stack. We perform ATOM on a BC-IoT testbed based on private Ethereum and Hyperledger Burrow. The experimental results highlight that, ATOM is more efficient than state-of-the-art approaches. ATOM can reduce update latency by 62.7%, ledger size by 70% and gas usage by 90% on average, respectively. Compared with the traditional smart contract architecture, ATOM can improve EVM Memory access efficiency significantly by up to 10x and achieve improvement of execution efficiency with up to 1:6x.

The security of hardware intellectual properties (IPs) has become a significant concern, as the opportunity for piracy, reverse engineering, and malicious modification is increasing. Hardware obfuscation has been studied as a potent method to protect against all these attack vectors. However, most of the existing obfuscation techniques have been successfully compromised, where many inherent functional or structural vulnerabilities in these techniques are utilized to reveal the obfuscation key or retrieve the original design. In this paper, we introduce LeGO, a learning-guided obfuscation framework that overcomes known vulnerabilities in a scalable and systematic manner, leading to a robust and lightweight locking mechanism. The proposed framework is guided by our security evaluation process that performs a thorough assessment of an obfuscated IP against various attacks and identifies the vulnerabilities. It then judiciously selects and applies a set of design modification steps or rules that can eliminate these vulnerabilities. Such a rule-based obfuscation process has the distinctive capability to address all existing as well as emerging attacks through the learning of appropriate design transformation steps that prevent these attacks. We present an efficient strategy to apply these rules on a design, while resolving any conflict. Our evaluation of the LeGO framework on a set of ISCAS85 and open-source IP benchmarks has shown promising results in terms of robustness against diverse attacks with an average of area, power and delay overhead of 39%, 45%, and 15%, respectively.

Power cables installed underneath the bridge have become vital in the cross-sea power transmission system. The design of grounding system is a decisive factor which determines the safety and reliability of these cables. In this paper, the nodal admittance matrix of the cable system is established considering the influence of the overhead laying condition and the coupled line model is used to improve the calculation efficiency. A matrix solution method, which can greatly reduce the dimension of the nodal equation, is proposed for the steady-state analysis of the grounding system. The grounding system designed for 220 kV cable project of Zhoudai Bridge in Zhejiang Province of China is also investigated. The results show that, compared with the induced voltage, the circulating current is the main factor affecting the ampacity of the cable system. Connecting the impedance at the cable joint can effectively reduce the power loss caused by circulating currents. A guideline for the grounding system design of the power cable lines installed underneath a bridge is proposed in this paper.

The hybrid dc circuit breaker is one of the most promising dc circuit breakers (DCCBs). However, its cost is relatively high, and the completion of its fault isolation is significantly delayed because of the large current limiting inductors configured in the multi-terminal dc grid. Besides, due to the utilization of overhead lines, the probability of temporary faults is much increased, which means there is a great possibility that the power supply can be rapidly restored by reclosing DCCBs. However, the temporary faults must be distinguished from the permanent faults before the reclosing operation to avoid damaging the fragile power electronic equipment. Therefore, considering the above issues, a novel multiport hybrid dc circuit breaker (MHCB) is proposed in this paper. The MHCB mainly has three advantages: the reduced implementation cost by sharing the expensive main breaker among multiple lines, the reduced fault isolation time by bypassing the current limiting inductor during energy dissipation, and the ability to reclose softly. Extensive simulations and experiments verify the effectiveness of the device. In addition, the comparison of the new device and existed solutions is presented.

Fault-injection attacks have become a major concern for hardware designs, primarily due to their powerful capability in tampering with critical locations in a device to cause violation of its integrity, confidentiality, and availability. Researchers have proposed a number of physical and architectural countermeasures against fault-injection attacks; however, these techniques usually come with large overhead and design efforts making them difficult to use in practice. In addition, the current electronic design automation (EDA) tools are not fully equipped to support vulnerability assessment against fault-injection attacks at the design-time for secure hardware development. To perform a design-time (i.e., pre-silicon) evaluation of such attacks, a designer should be aware of various security vulnerabilities and must perform a tedious manual design review, which is timeconsuming and hard to ensure effectiveness. Therefore, it is very important to develop an automatic assessment framework to identify the most security-critical locations in a design to fault-injection attacks and place emphasis on protecting those locations. In this paper, we propose an automated framework for fault-injection vulnerability assessment of designs at gate-level, while considering the design-specific security properties using novel models and metrics. The proposed framework identifies the faults that can violate the security properties of the design. As a result, applying local countermeasures will be more effective and the protection overhead will be reduced significantly. Our experimental results on the security properties of AES, RSA, and SHA implementations show that the security threat from fault-injection attacks can be significantly mitigated by protecting the identified critical locations, which are less than 0.6% of the design.

This brief presents SRAM write assist circuit using cell supply voltage self-collapse with bitline charge sharing (SC-BCS) that can lower the minimum operating voltage to the near-threshold voltage (Vth) region while consuming a minimal write energy. The proposed SC-BCS improves the write-ability by utilizing the cell supply voltage (CVDD) self-collapse and the feedback operation through the detection of write failure. Because the amount of CVDD collapse is regulated automatically depending on the write-ability of the selected cell, the write energy of the proposed SC-BCS is effectively reduced. The proposed SC-BCS can achieve a 5σ write-ability yield with a smaller delay overhead than gate-modulated self-collapse and self-collapse write assists in the near-Vth region. In addition, the proposed SC-BCS consumes the lowest write energy with minimal delay overhead or without any delay overhead compared with the strong-bias transient CVDD collapse and pulsed-pMOS transient CVDD collapse. The measurement result of the test chip fabricated using 65-nm CMOS technology indicates that the proposed SC-BCS can operate without any failure up to 0.36 V consuming write power 12.6 μW/MHz.

The integration of overhead lines in future MTDC grids leads to a higher fault rate compared to cables. Most of the faults are con-sidered to be non-permanent, so that the line can be recon-nected after dielectric recovery. The auto-reclosing procedure in HVDC systems reveals new challenges since multiple restrikes are possible within a short period of time. This paper proposes an auxiliary circuit for DC Circuit Breakers (DCCB) which enables to use the DCCB internal capacitor for the line pre-energization. A comprehensive description of the switchgear operations during the pre-energization sequence is provided and the fault property identification method is defined. The method is validated by simulations in a MTDC grid and a sensitivity analysis is carried out using EMTP-RV.

Green communications have always been a target for the information industry to alleviate energy overhead and reduce fossil fuel usage. In the current 5G and future 6G eras, there is no doubt that the volume of network infrastructure and the number of connected terminals will keep exponentially increasing, which results in the surging energy cost. It becomes growing important and urgent to drive the development of green communications. However, there is no doubt that 6G will have increasingly stringent and diversified requirements for Quality of Service (QoS), security, flexibility, and intelligence, all of which challenge the improvement of energy efficiency. Moreover, the dynamic energy harvesting process, which will be widely adopted in 6G, further complicates the power control and network management. To address these challenges and reduce human intervention, Artificial Intelligence (AI) has been extensively recognized and acknowledged as the only solution. Academia and industry have conducted extensive research to alleviate energy demand, improve energy efficiency, and manage energy harvesting in various communication scenarios. In this paper, we present main considerations for green communications and survey related research on AI-based green communications. We focus on how AI techniques are adopted to manage networks and improve energy efficiency towards the green era. We analyze how Machine Learning (ML) techniques including state-of-the-art Deep Learning (DL) can cooperate with conventional AI methods and mathematical models to reduce the algorithm complexity and improve the accuracy rate in 6G. Finally, we discuss the existing problems and envision the open research issues of AI models towards green 6G.

The development of cover conductors involving nano-hybrid polymers possessing high strength & good insulation properties would really help the electrical industry to avoid fatal accidents due to electrical shock and minimize electrical damage occurring due to short circuit in the event of tree/load falling on the bare overhead lines/conductors. The material selection and design are very essential parameters from the point of manufacturing, processing and application. The material characteristics dictate the mechanical as well as electrical performance in the field. For any material to have long life expectancy, compositions/constituents matter a lot with the combination of the basic raw materials. When any material such as overhead conductor is subjected to heavy electrical & mechanical loads, there is a likelihood of sag in the line and short circuit in the event of bare conductors resulting in fire. In such cases, the propagation of fire, fire retardancy, generation of smoke in addition to line protection are required to be considered from the point of life saving and system reliability. In this context, the electrical properties get affected due to varying loads acting on the conductor from time to time and depend on the season. As a part of remedial measures, cover conductor is best suited to meet the requirements. The design of the cover conductor shall be done in such a way that it meets the requirement of the prevailing standards. In the present work simulation studies will be performed using simulation software to study the behavior of electric field of nano based covered conductor and prove that these conductors will give better reliability and superior performance compared to the existing bare conductor. Further, the matrices and filler addition are envisaged are Acrylonitrile Butadiene Styrene (ABS)/Polytetrafluoroethylene (PTFE) of different combinations and nano-silica/nano-clay as fillers for the preparation of nano insulating covered conductor material.

Cable current detection plays a vital role in power grids toward improving transmission efficiency, relieving power congestion, and ensuring grid reliability. However, the sensors in existing current detection systems either are wired with measurement instruments or are wireless yet require batteries, which is inconvenient for monitoring overhead powerlines. Inspired by RF sensing tags, which are widely used for applications such as temperature and humidity measurements, in this article, we propose a distinctive cable current detection system that can avoid the constraint of wires and batteries. By detecting the ambient magnetic field produced by ac current flowing through a cable, the proposed system realizes a minimal measurement range of 5–17.5 A at 50/60 Hz with a maximum wireless distance of 5.2 m. This prototype can detect cable current with an extendable measurement range, providing a promising strategy for passive and wireless current detection.

With the increasing demand for large capacity power transmission over long distance, the use of overhead lines is required, which greatly increases the probability of temporary faults. After the faulty line is isolated by hybrid DC circuit breakers (HCBs), the power supply can be restored immediately by reclosing them in the event of temporary fault. However, fragile semiconductor switches will undergo two consecutive faults after the reclose of HCBs when permanent fault occurs. Therefore, a reclosing scheme is proposed in this paper to avoid the non-selective reclose of HCBs, whose core principle is an identification method of the instantaneous and the permanent faults. By controlling semiconductor switches in HCB, traveling wave signal is injected into the DC line. Then, whether the fault exists on the line can be determined by the difference in propagation characteristics of the injected signal. The effectiveness of the proposed reclosing scheme is verified by both point-to-point and four-terminal HVDC test systems based on modular multilevel converter built in PSCAD/EMTDC platform. Extensive simulations show that it is robust to fault resistance, etc., and has no identification dead zone. Besides, it has little impact on the healthy part of the system even the permanent fault occurs.

Physically Unclonable Functions (PUFs) are a promising technology and have been proposed as central building blocks in many cryptographic protocols and security architectures. Among other uses, PUFs enable chip identifier/authentication, secret key generation/storage, seed for a random number generator and Intellectual Property (IP) protection. Field Programmable Gate Arrays (FPGAs) are re-configurable hardware systems which have emerged as an interesting trade-off between the versatility of standard microprocessors and the efficiency of Application Specific Integrated Circuits (ASICs). In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in order to exploit the propagation delay differences of signals caused by manufacturing process variations. PUF technology can protect the individual FPGA IP cores with less overhead. In this article, we first provide an extensive survey on the current state-of-the-art of FPGA based PUFs. Then, we provide a detailed performance evaluation result for several FPGA based PUF designs and their comparisons. Subsequently, we briefly report on some of the known attacks on FPGA based PUFs and the corresponding countermeasures. Finally, we conclude with a brief overview of the FPGA based PUF application scenarios and future research directions.

5G and beyond mobile systems target a plethora of emerging industrial and entertainment verticals that incur extra overhead to the network. These verticals are characterized by vigorous, continuous, and conflicting requirements that make the desired system's mission strenuous and more challenging. These verticals, such as autonomous driving, will accommodate immersive services, including virtual reality/augmented reality (VR/AR) and Holography services. Immersive services, in particular, have strict requirements for latency, throughput, and positioning. This article discusses VR-based remote services' potential, which occupies an important place among immersive services such as remote surgery, remote space control, and remote driving of Unmanned Aerial Vehicles (UAVs) or cars. Such services require an ultra-low Glass-to-Glass latency to avoid any failure and accidents when remotely controlling devices. We evaluate an immersive remote control service from the end-to-end communication perspectives using different camera devices that stream real-time 360° videos to a VR Head Mounted Device (HMD). The obtained results demonstrate the challenges of such service and the need for more advanced and optimized techniques, devices, and protocols to achieve less than 20 ms of Glass-to-Glass latency.

Transmission lines are one of the most important components of a Power System. Overhead transmission lines run for hundreds of kilometres to supply power to the cities. At the same time, these lines are very susceptible to damage due to myriad reasons which include natural causes like particle contamination or technical reasons such as insulation failures, which do not immediately lead to a fault but lead to a phenomenon known as partial discharge (PD). Partial discharge is a localized dielectric breakdown which does not completely bridge the space between the two conductors in a small portion of a solid or liquid electrical insulation system under high voltage stress. Partial discharges slowly deteriorate the condition of the power line and, if left unrepaired, can lead to potential faults. Partial discharges are also a proven way of diagnosing the condition of power cables. This paper describes an approach towards detecting partial discharge signal patterns using machine learning algorithms and hence, predicting potential faults. The model described in this paper was able to detect PD patterns with 97% accuracy.

Solar energy is one of the most promising energy types, but photovoltaic (PV) mismatches have several negative effects. Finding an efficient and low-cost method to reduce or eliminate the power loss caused by the mismatch in PV power generation systems is necessary. In this paper, we propose a PV submodule-distributed maximum power point tracking (DMPPT) scheme based on a multi-port DC converter. In-depth analysis and research are performed on the PV model and mismatch characteristics, the PV module voltage equalization (VE) strategy, and implementation with the multi-port buck–boost converter. We discuss the trade-off between true DMPPT and VE on control overhead and tracking accuracy, and a detailed derivation is created to illustrate the differences between them. The VE can reduce the cost and complexity of the system at the expense of a small PV energy capture. The proposed implementation reduces the number of semiconductor components and current sensors, which is conducive to the integrated design of the hardware. A prototype based on a multi-port buck–boost converter for a 36 V/200 W PV module was designed and built. The feasibility and progress of the proposed scheme were verified through experiments.

Fast and accurate performance estimation can significantly enhance the efficiency of automated analog circuit synthesis. This article presents a novel performance modeling method that can efficiently estimate circuit performance with ignorable model building overhead for variant circuit topologies. The proposed method starts with accurate transistor modeling by taking advantage of the advanced neural network (NN) fitting technique. It then utilizes the established transistor models and topology information from a circuit netlist to precisely discover the circuit dc operating point. Specialized deterministic schemes have been developed with the aid of an undirected bipartite graph converted from the circuit netlist. Moreover, the accurate NN transistor models help directly derive the small-signal model parameter values, which can be further applied to conduct symbolic analysis to evaluate circuit performances. Our experimental results not only compare various deterministic dc operating point computation schemes but also demonstrate the efficient model development, general applicability, speedy execution, and fair prediction of our proposed performance modeling method.

The popularity of algebraic effect handlers as a programming language feature for user-defined computational effects is steadily growing. Yet, even though efficient runtime representations have already been studied, most handler-based programs are still much slower than hand-written code. This paper shows that the performance gap can be drastically narrowed (in some cases even closed) by means of type-and-effect directed optimising compilation. Our approach consists of source-to-source transformations in two phases of the compilation pipeline. Firstly, elementary rewrites, aided by judicious function specialisation, exploit the explicit type and effect information of the compiler’s core language to aggressively reduce handler applications. Secondly, after erasing the effect information further rewrites in the backend of the compiler emit tight code. This work comes with a practical implementation: an optimising compiler from Eff, an ML style language with algebraic effect handlers, to OCaml. Experimental evaluation with this implementation demonstrates that in a number of benchmarks, our approach eliminates much of the overhead of handlers, outperforms capability-passing style compilation and yields competitive performance compared to hand-written OCaml code as well Multicore OCaml’s dedicated runtime support.

The principles and methods of forming a comfortable lighting environment of reading rooms and bookstores of libraries by means of natural light are considered. Examples of the use of the "overhead" system in world practice are given. The factors influencing the quality of natural lighting of library premises and buildings are determined.

Recently, energy harvesting systems that utilize hybrid NVM-SRAM memory in their designs are introduced as a promising alternative for battery-operated systems. Since the ambient input power of an energy harvesting system fluctuates as the environmental conditions change, the system may stop the execution of programs until it receives enough energy to continue the execution. Resuming the execution of a program after the suspension may lead to data inconsistency in an energy harvesting system and threatens the correct functionality of the programs. In this paper, we propose COACH, an energy-efficient consistency-aware memory scheme which guarantees the correct functionality and consistency of the program in an energy harvesting system. The experimental results show that COACH improves forward-progress of the programs in the system by up to 60% compared with the state of the art consistency-aware approaches without imposing considerable energy overhead to the system.

On-chip electrostatic discharge (ESD) protection is becoming more challenging for integrated circuits (ICs) made in advanced technology nodes. The ESD-induced design overhead, including ESD parasitic effects and layout area, inherent to the traditional in-Silicon PN-junction-based ESD protection devices, rapidly becomes unbearable to high-performance and complex ICs. A disruptive above-Si mechanical ESD switch device, made in CMOS backend using a graphene nano-electromechanical-system (gNEMS) structure, was recently devised and demonstrated using poly-crystalline graphene films. This paper reports design, fabrication and comprehensive characterization of single-crystalline gNEMS ESD switch devices. Measurement using transmission line pulse (TLP) and very fast transmission line pulse (VFTLP) ESD testing reveals superior ESD protection capability of gNEMS devices made in single-crystalline graphene over its poly-crystalline counterparts, achieving a record-high ESD current handling capability of ${\text{I}}_{t2} {\sim }1.19 {\times }10^{10}\text{A}$ /cm2 under TLP zapping and ${\text{I}}_{t2} {\sim }6.09{\times }10^{9}\text{A}$ /cm2 under VFTLP stressing. The ESD robustness enhancement related to single-crystalline graphene material property is discussed.

Electronic shelf labels (ESL, or electronic price tag) are used by retailers for displaying product pricing on shelves substituting printed price tags; each ESL can display not only the price, but also text, and images, and can be remotely updated, configured, and programmed from a central server. Additionally, the emerging IoT paradigm, allows to expand the application horizon. Firstly, this work presents an analysis on how the use of Cloud-connected, intelligent, ESLs can improve food logistics in the complex scenarios of medium and large cities. Then, a low-cost ESL device, using an electronic ink (e-ink) display and the LoRaWAN protocol to communicate with the central server, aimed at price display and innovative applications in food retail and logistics, is presented. Several current consumption and communication distance measurements are shown, and the design and configuration space are explored to optimize battery life and communication reliability in the different food distribution scenarios. The proposed ESL is powered with a 500mA $\cdot \text{h}$ LiMnO2 battery that can last for >8 years in a typical application, considering it communicates with a central server once per hour. The developed price tag can dynamically update the price and information for the customer, which in the case of food can be used to minimize spoilage and can easily upgraded to incorporate sensors or smartphone interaction to develop innovative food logistics and marketing practices. Finally, a LoRaWAN time-slot allocation strategy is presented, to minimize collisions when thousand nodes are connected to a single gateway, with a minimum power consumption overhead.

High leakage power consumption has become a serious problem in modern IC designs. By isolating a circuit block that is not in use from the power supply, power gating has become one of the most effective ways to reduce leakage power. During the circuit wake-up process, turning on sleep transistors simultaneously may induce an excessive surge current, which will threaten signal integrity. To avoid significant surge currents, sleep transistor wake-up sequences should be carefully designed. On the other hand, PMOS sleep transistors may suffer from the Negative-Bias Temperature Instability (NBTI) effect, where the wake-up time is increased after circuit aging. Conventional fixed wake-up sequence-based methods do not consider the NBTI effect, which may result in a longer or an unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel reconfigurable circuit structure that can reconfigure the wake-up sequence and a novel NBTI-aware wake-up strategy to reduce the wake-up time. Our strategy first finds a set of proper wake-up sequences under different aging circumstances and then dynamically reconfigures wake-up sequences at runtime based on an actual aging scenario (i.e. different months or years of aging). The experimental results show that compared with a traditional fixed wake-up sequence approach, our strategy can reduce up to 49.78% of the average wake-up time latency. In the meantime, according to our estimation, to implement the reconfigurable wake-up sequence structure, the parasitic area overhead is only about 0.27% with a larger benchmark.

Noisy intermediate scale quantum (NISQ) computers are becoming a reality thanks to the recent advances made by researchers who physically build such systems. In order to execute corresponding quantum algorithms (usually provided in terms of quantum circuits), certain physical constraints in the architectures need to be satisfied. More precisely, physical constraints restrict the possible interactions between qubits which frequently result in cases where qubits which are supposed to interact in a quantum circuit are not allowed to interact on the physical device. Thus far, this is addressed by dedicated methods that map the logical quantum circuit to a physical realization and satisfy the constraints by inserting further operations. This leads to additional costs which harm the fidelity of the circuit and, hence, urgently need to be avoided. Unfortunately, current state-of-the-art approaches for this mapping process take the existing architectures as invariant and only try to reduce the number of additionally needed operations. In contrast, (slight) changes in the, respectively, given architectures (which still keep the underlying physical constraints satisfied) might be possible and may allow for even better (i.e., less costly) mappings. But this potential has not been investigated yet. In this work, we explore this potential. More precisely, we introduce several schemes for generating alternative coupling graphs (and, by this, quantum computing architectures) that still might be able to satisfy physical constraints but, at the same time, allow for a more efficient realization of the desired quantum functionality. Evaluations confirm the potential of those alternative coupling graphs and demonstrate that they can reduce the mapping overhead by up to 60% in the best case and up to almost 40% on average.

The hardware security of RSFQ circuits has become an issue of growing importance for prospective exascale computing systems. Hardware security in RSFQ circuits is particularly relevant to large scale data centers operating with sensitive information. The number of fabrication facilities for superconductive niobium-based technology is limited, and the supply chain for distributing fabricated circuits can be compromised. Logic locking is widely used in modern CMOS circuits to enhance security by masking the functionality of the circuit using a secret key. If an attacker possesses a physical circuit secured by logic locking, the attacker would be unable to determine the intended function. In this paper, a novel methodology for logic locking is proposed for SFQ circuits. Mutual inductances are used to apply additional currents to some or all of the logic gates. These currents behave as keys to access the functionality of the SFQ logic elements. In the proposed technique, only after an additional correct current is applied to all of the locked gates will the circuit produce the proper output. By using inductors with a positive and negative mutual inductance connected to the internal inductances of the gates, the range of current required to unlock a secured circuit is greatly narrowed. In this work, the operation of this proposed logic locking technique is demonstrated using modified SFQ OR gates to enable security while maintaining proper functionality. Less than 4% area overhead is achieved.

The purpose of the article is to analyze the damage rate of overhead power transmission lines (OPL) in medium-voltage electrical distribution networks of the Irkutsk region. The established International Indices that determine the level of reliability of the functioning of electric networks are considered, and information on the compliance of the condition of electric networks in Russia with these indices is analyzed. Analytical information on the damage rate of elements of these networks and their causes in Europe, America, and Russia is presented. The emphasis is placed on the fact that the most common damage is characteristic of overhead power lines, especially 6–10 kV lines. As an object of research, two branches of the Irkutsk electric grid company (IEC) were taken, one of which provides electricity to rural consumers, the other — mainly to consumers residing in the territory of the city Irkutsk. The characteristics of these electric networks, their territorial location and basic technical data are presented. To conduct analytical monitoring of the level of reliability of overhead power transmission lines, logs of disconnection of the Eastern and Southern electric networks of the IEC over a long-term period were used. On the basis of this information, tables of failures and their consequences in the studied electrical networks were compiled for monthly average data over the period under examination for various causes of damage. To plot time diagrams of the parameters under examination, computer programs were compiled in the Matlab system, the use of which made it possible to obtain visualization of changes in failures for various reasons for the electrical networks under consideration. The information on the time of power supply interruptions in these networks, as well as the amount of electricity underutilized by consumers during these interruptions and its cost are analyzed. It is shown that in the electric networks under consideration, most of the power failures are related to the territorial dispersion of these networks, and the low level of equipment controls and insufficient qualification of operating personnel, as evidenced by the significant number of failures for unknown reasons. Besides, a significant part of the failures is due to damage to the overhead line wires, switching equipment and the effect of wind load. Recommendations for improving the condition of power transmission lines and a number of measures aimed at improving the level of reliability of power supply are presented.

The establishment of smart grids requires special attention to the safety of power industry facilities and the reduction in their negative impact on personnel and the environment. A significant factor of such an impact is the considerable intensities of electromagnetic field (EMF) generated by such facilities. In the context of power industry digitalization, the development of methods and tools for EMF digital simulation is needed to ensure the electromagnetic safety of the service personnel. Computer models designed to adequately determine the EMF generated by overhead power lines (OPL) can be implemented based on the methods and tools created to determine operating parameters of electric power systems in phase coordinates developed at Irkutsk State Transport University. The technique of electromagnetic safety analysis is implemented based on the proposed approach and has the following features: a systems approach, which is the possibility of simulating electromagnetic fields in terms of properties and characteristics of a complex electric power system; versatility, which allows simulating power lines and traction networks of various designs; appropriateness to the environment achieved by considering the profile of the underlying surface, underground utilities, and artificial structures of rail transport, such as galleries, bridges, and tunnels; comprehensiveness, which is provided by combining the computation of operating parameters and the determination of EMF intensities. The paper describes methods and algorithms developed to determine the intensities of electromagnetic fields generated by multi-conductor power lines at fundamental and higher harmonics frequencies. A technique for the EMF determination at the points of OPL orthogonal crossing is also presented.

Utilizing heterogeneous accelerators, especially GPUs, to accelerate machine learning tasks has shown to be a great success in recent years. GPUs bring huge performance improvements to machine learning and greatly promote the widespread adoption of machine learning. However, the discrete CPU-GPU architecture design with high PCIe transmission overhead decreases the GPU computing benefits in machine learning training tasks. To overcome such limitations, hardware vendors release CPU-GPU integrated architectures with shared unified memory. In this article, we design a benchmark suite for machine learning training on CPU-GPU integrated architectures, called iMLBench, covering a wide range of machine learning applications and kernels. We mainly explore two features on integrated architectures: 1) zero-copy, which means that the PCIe overhead has been eliminated for machine learning tasks and 2) co-running, which means that the CPU and the GPU co-run together to process a single machine learning task. Our experimental results on iMLBench show that the integrated architecture brings an average 7.1× performance improvement over the original implementations. Specifically, the zero-copy design brings 4.65× performance improvement, and co-running brings 1.78× improvement. Moreover, integrated architectures exhibit promising results from both performance-per-dollar and energy perspectives, achieving 6.50× performance-price ratio while 4.06× energy efficiency over discrete GPUs. The benchmark is open-sourced at https://github.com/ChenyangZhang-cs/iMLBench .

At present, on the territory of the Russian Federation, there is no massive use of electrically conductive reinforced concrete structures in the electric power industry due to insufficient operating experience and a low rate of research on electrically conductive concretes. The article compares the main characteristics of existing electrically conductive concrete. The paper shows the disadvantages of traditional concrete and existing electrically conductive concrete. The electrically conductive concrete was selected, the most suitable for further research, testing and direct modernization of the composition based on the results obtained. The main disadvantages of existing electrically conductive concretes are the high cost and specificity of electrically conductive components and other additives, as a consequence of the amount of capital investment in mass and large-scale production, as well as the lack of operating experience as overhead supports.

The fast development of Blockchain technology makes it widely applied in several fields of digital transactions, like e-government affairs and the protection of financial transactions. In this article, we propose a homomorphic encryption-based Blockchain for circuit copyright protection that effectively addresses the issues in the protection of circuit copyright transactions, such as low security of private data, low efficiency in transaction data storage, cooperation and supervision. First, we establish a homomorphic encryption-based mathematical model by utilizing Blockchain and intelligent contract, and next, the algorithms that include Blockchain generation, homomorphic chain encryption/decryption, and intelligent contract are designed. As the intelligent contract is correctly executed in Blockchain, a fully homomorphic encryption-based identity authentication protocol is tackled for Blockchain, given that it ensures the change operation of any third-party in Blockchain and realizes real-time verification. The system is apposite for circuit copyright protection in a blockchain network, due to the use of distributed identity authentication and real-time extensible storage improves the security and extensibility of blockchain-based circuit copyright protection. The experimental results show that the proposed algorithm has reduced the transmission cost and improved the efficiency of data storage and supervision. In addition, it is resilient to several common attacks (e.g., double-spending attacks), yet incurs low cost/overhead and has a higher level of security when compared to three other competing algorithms.

Software verification is an important stage of the software development process, particularly for mission-critical systems. As the traditional methodology of using unit tests falls short of verifying complex software, developers are increasingly relying on formal verification methods, such as explicit state model checking, to automatically verify that the software functions properly. However, due to the ever-increasing complexity of software designs, model checking cannot be performed in a reasonable amount of time when running on general-purpose cores, leading to the exploration of hardware-accelerated model checking. FPGAs have been demonstrated to be promising verification accelerators, exhibiting nearly three orders of magnitude speedup over software. Unfortunately, the “FPGA programmability wall,” particularly the long synthesis and place-and-route times, block the general adoption of FPGAs for model checking. To address this problem, we designed a runtime-programmable pipeline specifically for model checkers on FPGAs to minimize the “preparation time” before a model can be checked. Our design of the successor state generator and the state validator modules enables FPGA-acceleration of model checking without incurring the time-consuming FPGA implementation stages, reducing the preparation time before checking a model from hours to less than a minute, while incurring only a 26% execution time overhead compared to model-specific implementations.

System integrators create heterogeneous systems-on-chip (SoCs) by integrating numerous third-party intellectual property blocks (3PIPs) to achieve application-specific design goals. With increasing intellectual property (IP) complexity, 3PIPs can suffer from hardware bugs or they can inadvertently introduce other software-exploitable security threats to the SoC. To ensure the ongoing survivability of new SoCs, we need infrastructure for patching newly discovered IP issues after an SoC has been deployed. To address the increasing risks from 3PIPs, we explore the feasibility and limitations of implementing monitoring and mitigation capabilities in hardware. Our proposed monitoring and mitigation patch (MoP) blocks provide a defensive foundation against critical IP-centric issues, focusing on situations where a system integrator only has interface-level visibility of 3PIP designs. The MoPs are distributed throughout the SoC to monitor and mitigate issues directly in hardware and transparently for potentially compromised software—the MoPs are resilient against run-time compromised software and firmware. We ensure that these monitors are reconfigurable after deployment by implementing them using embedded-FPGAs or as a reprogrammable, fixed-design module. We perform a case study of numerous IP-types and model a selection of security-relevant issues and bugs in the IPs, exploring the relative complexity and potential resource overhead. Our study shows the utility of our proposed approach, with MoP blocks requiring less than ~1.5% of the adaptive logic modules (ALMs) in a Cyclone V FPGA for interface monitoring and issue mitigation per IP.

The use of through silicon vias (TSVs) is essential for vertically connecting the individual circuit layers of a 3-D IC. However, because the pitch between TSVs is being decreased, it becomes more vulnerable to bridge defects between the TSVs. In the previous architectures, the parallel topology between the power supply and the bridge defects reduces the resolution of the test results and makes them very sensitive to process variations. In this article, an enhanced postbond test architecture that improves the testability of bridge defects screening with a floating control circuit of supply voltage driver is proposed. The proposed structure allows the selective formation of a series circuit that includes the supply voltage driver and bridge defects between the TSVs; the structure can improve the output voltage resolution of the bridge defects by 27.2 times over that of the previous architectures. According to the experimental results, while exhibiting a proper test time, hardware overhead, and peak current consumption for mass production, the system guarantees testability for the detection of bridge defects. Moreover, the Monte Carlo simulation results show that the proposed architecture has a higher test reliability under process variations than the current test architectures.

Nowadays, there has been an intensive increase in embedded systems complexity. So that optimization and performance development become an interesting topic to study. In this proposal, the main problem to solve is to make the possibility to get more flexibility, to reduce cost and to improve performance. Considering this fact, we introduce in this paper a reconfigurable component integrated into Cortex M0 based System on Chip (SoC) which has the form of embedded FPGA. To the best of our knowledge, this is the first reconfigurable SoC composed of Tree-based embedded FPGA. Besides, we explored the different ways to reach the integration and the different steps. Then, we compared reconfigurable SoC with another developed SoC which contains many hardware accelerators which are a set of popular benchmarks in terms of performance and area. Finally, we take a popular error correction algorithm “RS-Encoder” as a test case. We made the profiling of this software application in order to compare the reconfigurable SoC with a classic SoC in terms of run-time. Preliminary results were presented and showed that the eFPGA integration introduces a chip area overhead but it proves interesting results in terms of run-time. Indeed, for 100 software instructions, the eFPGA is faster 4 times compared to a hardware accelerator and 412 times compared to the software implementation of the RS Encoder application.

A continuous-rate referenceless clock and data recovery (CDR) circuit with an unlimited frequency acquisition capability is presented. The proposed frequency detector (FD) is derived from a multi-phase oversampling FD. Through accurate analysis of the root causes limiting the capture range, the extension techniques are proposed and digitally implemented by a small hardware overhead. The FD achieves the unlimited frequency detection capability and exhibits robust operation regardless of the initial clock frequency. The effect of the quadrature error is analyzed and verified by simulation. In addition, a frequency lock detector is implemented to control the loop gain for fast frequency acquisition. The prototype CDR circuit was designed and fabricated in a 65-nm CMOS process, occupying an active area of 0.045 mm2. The CDR circuit achieves a capture range from 4 Gb/s to 20 Gb/s, which is limited only by the oscillator operating range. The worst case acquisition time is 25 $\mu \text{s}$ with a PRBS31 pattern. The CDR circuit achieves a BER less than 10−12 and an energy efficiency of 1.87 pJ/b.

Cloud computing has begun a transformation from using virtual machines to containers. Containers are attractive because multiple of them can share a single kernel, and add minimal performance overhead. Cloud providers leverage the lean nature of containers to run hundreds of them on a few cores. Furthermore, containers enable the serverless paradigm, which leads to the creation of short-lived processes. In this work, we identify that containerized environments create page translations that are extensively replicated across containers in the TLB and in page tables. The result is high TLB pressure and redundant kernel work during page table management. To remedy this situation, this paper proposes BabelFish, a novel architecture to share page translations across containers in the TLB and in page tables. We evaluate BabelFish with simulations of an 8-core processor running a set of Docker containers in an environment with conservative container co-location. On average, under BabelFish, 53% of the translations in containerized workloads and 93% of the translations in serverless workloads are shared. As a result, BabelFish reduces the mean and tail latency of containerized data-serving workloads by 11% and 18%, respectively. It also lowers the execution time of containerized compute workloads by 11%. Finally, it reduces serverless function bring-up time by 8% and execution time by 10%-55%.

With the increasing popularity and applications of 2.5-D integration, both chip and packaging industries are making significant progress in this direction. In advanced high-density 2.5-D packages, package redistribution layers become similar to chiplet back-end-of-line routing layers, and the gap between them scales down with pin density improvement. Chiplet–package interactions become significant and severely affect system performance and reliability. Moreover, 2.5-D integration offers opportunities to apply novel design techniques. The traditional die-by-die design approach neither carefully considers these interactions nor fully exploits the cross-boundary design opportunities. In this article, we present a holistic chiplet–package co-optimization flow for high-density 2.5-D packaging technologies with little performance overhead and zero pipeline-depth increase. Our holistic extraction can capture all parasitics from chiplets and the package and improve system performance through iterative optimizations. Both drop-in and pay-as-you-use design methodologies are implemented for agile development and quick turn-around time. To prove the effectiveness of our flow, we implement several design cases of a microcontroller system in TSMC 65-nm technology. Our design methodologies can reduce the performance gap by 85% with respect to the 2-D reference design after holistic optimizations. We demonstrate design flexibility and development cost-saving by presenting several flavors of a three chiplets system. To validate our flow in silicon, we tape-out a chip in TSMC 65-nm technology with measured data and validated functionality.

The low-power chips are occurring test challenges on chip’s shmoo test on yield and performance degradation. A method for improving the performance-yield from adjusting the clock edge is presented. This work proposes a clock-edge adjusted circuit (CAC) to adjust the duty-cycle for testing multi-Vdd and multi-Vth circuits. Instead of adopting a phase-lock-loop to generate a clock with different frequencies, by external ATE cannot adjust chip-internal clock-frequency after a chip is manufactured. However, by using the proposed CAC circuit, the chip duty cycle can be trimmed. The proposed CAC generates an adjustable wide-range trigger-edge signal for the DUT chip, the duty cycles of the clock with a fixed frequency are adjusted to emulate a fast/slow chip-clock frequency. CAC can quickly push the circuit toward correct functional operation under at-speed shmoo-binning operations. It is an efficient with low-area overhead design-for–test circuit to support multi-Vdd/Vth complex designed chips. The CAC technique jointed with using Agilent-93000 automatic-test-equipment (ATE) is used to validate a four multi-Vdd/Vth Cortex-M0 processors chip. The measurements demonstrate yield improvement and accurate performance evaluation from using the CAC by ATE.

The OpenMP specification defines a set of compiler directives, library routines, and environment variables that together represent the OpenMP Application Programming Interface, and is currently defined for C, C++, and Fortran. The forthcoming version of Ada, currently dubbed Ada 202X, includes lightweight parallelism features, in particular parallel blocks and parallel loops. All versions of Ada, since its inception in 1983, have included "tasking," which corresponds to what are traditionally considered "heavyweight" parallelism features, or simply "concurrency" features. Ada "tasks" typically map to what are called "kernel threads," in that the operating system manages them and schedules them. However, one of the goals of lightweight parallelism is to reduce overhead by doing more of the management outside the kernel of the operating system, using a light-weight-thread (LWT) scheduler. The OpenMP library routines support both levels of threading, but for Ada 202X, the main interest is in making use of OpenMP for its lightweight thread scheduling capabilities.

Computationally intensive neural network applications often need to run on resource-limited low-power devices. Numerous hardware accelerators have been developed to speed up the performance of neural network applications and reduce power consumption; however, most focus on data centers and full-fledged systems. Acceleration in ultra-low-power systems has been only partially addressed. In this article, we present multiPULPly, an accelerator that integrates memristive technologies within standard low-power CMOS technology, to accelerate multiplication in neural network inference on ultra-low-power systems. This accelerator was designated for PULP, an open-source microcontroller system that uses low-power RISC-V processors. Memristors were integrated into the accelerator to enable power consumption only when the memory is active, to continue the task with no context-restoring overhead, and to enable highly parallel analog multiplication. To reduce the energy consumption, we propose novel dataflows that handle common multiplication scenarios and are tailored for our architecture. The accelerator was tested on FPGA and achieved a peak energy efficiency of 19.5 TOPS/W, outperforming state-of-the-art accelerators by 1.5× to 4.5×.

As CMOS devices become smaller, process and aging variations become a major issue for circuit reliability and yield. In this paper, we propose a new two-phase gate sizing approach in order to improve the reliability of the circuit considering the joint effect of process variation and transistor aging. In the first stage, the initial delay of the circuit is optimized to improve the timing yield of the circuit. Then, in the second stage, we reduce the delay degradation induced by aging and process variations. To this end, two novel concepts called aging probability and delay degradation-aware gate criticality are introduced which enable us to perform gate sizing efficiently using an adaptive multi-objective ranking approach. Experimental results based on ISCAS’85 and EPFL benchmark circuits show that, the proposed method achieves the 95 percent timing yield constraint and the 10 percent timing guard-band as the lifetime reliability constraint at the expense of 13.72 percent area overhead, on average. In comparison with the state-of-the-art methods, the proposed approach imposes lower area overhead with acceptable runtime.

As the traditional CMOS technology encounters significant scaling challenges, many emerging beyond-CMOS devices have been proposed and developed to augment or even replace CMOS devices. Spintronic devices have received extensive attention due to several unique attributes, including a low operation voltage and nonvolatility. However, spintronic devices are intrinsically slow because of the long switching delay of the magnet. To overcome the drawback, in this article, we propose and develop a deep pipeline method for generic spintronic majority-gate-based circuits. A fast and efficient pipeline buffer insertion methodology is integrated into the industry-standard placement and routing design flow to ensure the correct functionality. The proposed framework can accurately capture 1) the timing of a multiphase clock-gated spintronic circuit and 2) the energy overhead associated with the supply clocking, which is one major overhead of spintronic circuits. Based on the proposed framework, we demonstrate that a spintronic circuit implemented with a deep pipeline can provide over $10\times $ reduction in energy-delay products compared to their traditional CMOS-based counterparts. In the case study, the proposed deep pipeline method is applied to three emerging spintronic devices. Results show that device-level parameters have significant impacts on circuit-level performance and optimal logic depth.

Power grid failure is very costly to any modern society, and preventing upheavals like the blackout in eastern US and Canada in the summer of 2003 is extremely important. Complete power grid failure may be triggered by the failure of a transformer, underground cable, overhead line insulator or any other component of the power grid. While close monitoring of expensive, centrally located assets like transformers, generators and circuit breakers is feasible and economically justified, it is extremely difficult to continuously monitor assets that are spread over long distances, and in some cases very difficult to reach, like overhead lines accessories and outdoor insulators. Condition monitoring of outdoor insulators is prohibitively costly, time consuming and unsafe. To overcome these problems, the use of machine learning (ML) in outdoor insulators condition monitoring and diagnostics could be a viable solution.

We introduce maximum-likelihood fragment tomography (MLFT) as an improved circuit cutting technique for running clustered quantum circuits on quantum devices with a limited number of qubits. In addition to minimizing the classical computing overhead of circuit cutting methods, MLFT finds the most likely probability distribution for the output of a quantum circuit, given the measurement data obtained from the circuit’s fragments. We demonstrate the benefits of MLFT for accurately estimating the output of a fragmented quantum circuit with numerical experiments on random unitary circuits. Finally, we show that circuit cutting can estimate the output of a clustered circuit with higher fidelity than full circuit execution, thereby motivating the use of circuit cutting as a standard tool for running clustered circuits on quantum hardware.