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166 results on '"Ottavi, M."'

1. Un véritable piège artériel

Author

Bernigaud, C., primary, Barthelemy, G., additional, Caron, J., additional, Fassbender, V., additional, Jean-Baptiste, E., additional, Ottavi, M., additional, Lechtman, S., additional, Jeandel, P.Y., additional, Nihal, M., additional, Levraut, M., additional, and Merindol, J., additional

Published
2024
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2. Une allogreffe sanglante

Author

Barthelemy, G., primary, Lechtman, S., additional, Jeandel, P.Y., additional, Ottavi, M., additional, Bernigaud, C., additional, Caron, J., additional, Martis, N., additional, Merindol, J., additional, and Levraut, M., additional

Published
2024
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5. On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories

Author

Schiano, L., Ottavi, M., Lombardi, F., Pontarelli, S., and Salsano, A.

Subjects
Computer Science - Information Theory
Abstract

Single Event Upsets (SEU) as well as permanent faults can significantly affect the correct on-line operation of digital systems, such as memories and microprocessors; a memory can be made resilient to permanent and transient faults by using modular redundancy and coding. In this paper, different memory systems are compared: these systems utilize simplex and duplex arrangements with a combination of Reed Solomon coding and scrubbing. The memory systems and their operations are analyzed by novel Markov chains to characterize performance for dynamic reconfiguration as well as error detection and correction under the occurrence of permanent and transient faults. For a specific Reed Solomon code, the duplex arrangement allows to efficiently cope with the occurrence of permanent faults, while the use of scrubbing allows to cope with transient faults., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Published
2007

15. Fault tolerant solid state mass memory for space applications

Author

Cardarilli, G.C., Ottavi, M., Pontarelli, S., Re, M., and Salsano, A.

Subjects
Fault tolerance (Computers) -- Design and construction, Fault tolerance (Computers) -- Analysis, Fault tolerance, Aerospace and defense industries, Business, Computers, Electronics, Electronics and electrical industries
Abstract

In this paper an innovative fault tolerant solid state mass memory (FTSSMM) architecture is described. Solid state mass memories (SSMMs) are particularly suitable for space applications and more ill general for harsh environments such us, for example, nuclear accelerators or avionics. The presented FTSSMM design has been entirely based on commercial off the shelf (COTS) components. In fact, cost competitive and very high performance SSMMs cannot be easily implemented by using space qualified components, due the technological gap and very high cost characterizing these components. In order to match the severe reliability requirements of space applications a COTS-based apparatus must be designed by using suitable system level methodologies [1, 2]. In the proposed architecture error-correcting codes are used to strengthen the commercial dynamic random access memory (DRAM) chips, while the system controller has been designed by applying suitable fault tolerant design techniques. Different from other proposed solutions, our architecture fully exploits the reconfiguration capabilities of Reed-Solomon (RS) codes, discriminates between permanent and transient faults reducing the use of spare elements, and provides dynamic reconfiguration and graceful degradation capability, i.e., the FTSSMM performances are gracefully reduced in case of permanent faults, maintaining part of the system functionality. The papers shows the FTSSMM design methodology, the architecture, the reliability analysis, some simulation results, and a description of its implementation based on fast prototyping techniques.

Published
2005

17. Guest Editorial: IEEE Transactions on Emerging Topics in Computing Special Issue on Design & Technology of Integrated Systems in Deep Submicron Era

Author

Di Natale, G, Ottavi, M, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), and Università degli Studi di Roma Tor Vergata [Roma]

Subjects
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Settore ING-INF/01 - Elettronica
Abstract

International audience; The ten papers in this special section address issues related to the design, reliability, security and testing of integrated systems in the nanoscale era. These papers cover a wide spectrum of techniques, including the issues of low-power design, the test, the reliability, the security and trust of circuits manufactured with emerging technologies.

Published
2018
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20. MEMRISTOR BASED SENSOR

Author

Abusaleh, J, Ottavi, M, Jimson, M, Martinelli, E, DI NATALE, C, and Adedotun, A

Subjects
GOIN 27 / 12 GOIN 33 / 00, Settore ING-INF/01
Published
2017

22. Dependable Multicore Architectures at Nanoscale: the view from Europe

Author

Ottavi, M., Pontarelli, S., Gizopoulos, D., Paschalis, A., Bolchini, C., Michael, Maria K., Anghel, L., Tahoori, M., Reviriego, P., Bringmann, O., Izosimov, V., Manhaeve, H., Strydis, C., Hamdioui, S., Michael, Maria K. [0000-0002-1943-6547], University of Rome (UNIVERSITY OF ROME), Università degli Studi di Roma Tor Vergata [Roma], Department of Informatics and Telecomunications [Kapodistrian Univ] (DI NKUA), National and Kapodistrian University of Athens (NKUA), Virginia Commonwealth University (VCU), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Karlsruhe Institute of Technology (KIT), Forschungszentrum Informatik, CS Dep, Linköping University (LIU), The Current Test Company (Q-Star Test), Q-Star Test, Delft University of Technology (TU Delft), Neurosciences, Department of Informatics and Telecommunications (Athens), National and Kapodistrian University of Athens = University of Athens (NKUA | UoA), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
010302 applied physics, Multi-core processor, Engineering, business.industry, 02 engineering and technology, Settore ING-INF/01 - Elettronica, 01 natural sciences, Electronic mail, 020202 computer hardware & architecture, law.invention, Instruction set, Microprocessor, Hardware and Architecture, law, Multicore, Dependablity, Embedded system, PACS 85.42, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Software
Abstract

International audience; This article presented a survey of dependability issues faced by multi-core architectures at nanoscale technology nodes. Existing solutions against these challenges were also discussed, describing their scope of application, from technology level methodologies, to design approaches to the metrics required to evaluate the overall dependability of a system. In the future, the constant reduction of the feature size of the devices will exacerbate the issues related to aging and soft errors. This will create further challenges and at design level, an integrated design approach that will cope with the occurrence of faults at any time of their occurrence i.e., at manufacturing (thus increasing yield) and in the field (thus increasing reliability) will become more and more important to obtain economically viable and dependable systems. Dependability assessment will also need an integrated approach for cross-layer, pre- and post-silicon techniques for “just right”dependability assessment in order to avoid “overdesign”for dependability using classic guard-banding methodologies.

Published
2015
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23. Dependable multicore architectures at nanoscale: The view from Europe

Author

Ottavi, M. Pontarelli, S. Gizopoulos, D. Paschalis, A. Bolchini, C. Michael, M.K. Anghel, L. Tahoori, M. Reviriego, P. Bringmann, O. Izosimov, V. Manhaeve, H. Strydis, C. Hamdioui, S.

Abstract

The introduction of multicore chips allowed the constant increase in delivered performance otherwise impossible to achieve. Multiple microprocessor cores from different instruction set architectures stay at the epicenter of such chips and are surrounded by memory cores of different technologies, sizes and functionalities, as well as by peripheral controllers, special function cores, analog and mixed-signal cores, reconfigurable cores, etc. The functionality as well as the complexity of multicore chips is unprecedented. © 2015 IEEE.

Published
2015

24. Improving the Reliability of Skewed Caches through ECC based Hashes

Author

Yegin, S, Karsli, B, Ergin, O, Ottavi, M, Pontarelli, S, and Reviriego, P

Subjects
Hardware_MEMORYSTRUCTURES, Data_FILES
Abstract

Skewed caches have been proposed to reduce the miss ratio on a cache by indexing the cache lines of a two way set associative cache not with the index but with a hash function of the index and the tag. This paper proposes to use ECC codes as the hashing functions that allow also correcting the stored data. It is shown that ECC behave very well as hash functions and that ECC protection provides gains in terms of error coverage with respect to state of the art skewed cache approaches.

Published
2014

25. Error detection in ternary CAMs using bloom filters

Author

Salvatore Pontarelli, Ottavi, M., Evans, A., Wen, S. -J, Torella, Lucie, University of Rome (UNIVERSITY OF ROME), Università degli Studi di Roma Tor Vergata [Roma], Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Cisco Systems, CISCO Systems, Inc, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
010302 applied physics, PACS 8542, Hardware_MEMORYSTRUCTURES, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 01 natural sciences, Settore ING-INF/01 - Elettronica, 020202 computer hardware & architecture
Abstract

International audience; This paper presents an innovative approach to detect soft errors in Ternary Content Addressable Memories (TCAMs) based on the use of Bloom Filters. The proposed approach is described in detail and its performance results are presented. The advantages of the proposed method are that no modifications to the TCAM device are required, the checking is done on-line and the approach has low power and area overheads.

Published
2013

27. Tile-based QCA design

Author

Huang, J, Momenzadeh, M, Schiano, L, Ottavi, M, and Lombardi, F

Subjects
Settore ING-INF/01 - Elettronica
Published
2007

28. QCA Memory

Author

Vankamamidi, V, Ottavi, M, and Lombardi, F

Subjects
Settore ING-INF/01 - Elettronica
Published
2007

35. High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Author

Bolchini, C., primary, Miele, A., additional, Sandionigi, C., additional, Ottavi, M., additional, Pontarelli, S., additional, Salsano, A., additional, Metra, C., additional, Omana, M., additional, Rossi, D., additional, Reorda, M. Sonza, additional, Sterpone, L., additional, Violante, M., additional, Gerardin, S., additional, Bagatin, M., additional, and Paccagnella, A., additional

Published
2012
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