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The Field Soft Error Rate (FSER) has been determined by the variation of the critical charge and the measurement of the charge collection volume determined by alpha-particle irradiation. The modelled FSER versus critical charge dependence agrees well to the one of the Field Soft Error measurements. The results futher show, that the impact of the on-chip Alpha-Particle flux can be neglected.

The model allows the simulation of threshold voltage and drain current shifts as well as FN-tunnel and substrate currents caused by FN and band-to-band tunneling. This is achieved by determining the floating gate charge and voltage as function of time and short channel and geometry effects during programming, erasing and reading.

A BSIM3v3.1 based flash memory degradation compact model for circuit simulators has been developed. By a physics based modification of the Fowler-Nordheim equation, the tunnel current can be calculated considering both positive and negative oxide charges. It has been shown that every known endurance characteristic can be simulated by this model. It allows a precise simulation of worst case operation of flash memories and an optimized circuit design.

A physics based compact model describing the fatigue behavior of ferroelectric capacitors has been developed. Fatigue is a gradual decrease of detectable polarization with increasing number of polarization cycles. This can be caused by trapped charges which pin dipoles near the interface to the electrode. In order to polarize those pinned dipoles they have to be separated from the trapped charges by a higher electrical force. This force has been described in our model by additional coercive voltages representing the different polarization response of the dipoles in the interface region in contrast to those in the inner region of the ferroelectric capacitor. Our model has been implemented into a common-used circuit simulator showing good agreement with measurements.

A dynamic model has been developed that is based on the Preisach approach for ferroelectric capacitors. It accounts for different switching reaction of the dipoles dependent on the applied voltage gradients. A method for extracting the necessary parameters by measuring the coercive voltage versus applied frequency is provided. The model was verified by testing capacitors of different geometries. Excellent agreement was achieved between our measurements and the corresponding circuit simulations. The simulation of a FeRAM-cell with our new dynamic model shows that the bit line signal decreases substantially with fast read/write times.

To ensure a data retention time of e.g. 10 years a maximum allowed floating gate doping concentration can not be exceeded. The data retention time can be improved by reducing the floating gate doping concentration. This reduction causes a so far negligible depletion effect in the floating gate reducing the V T -shift by approximately 1.5 Volts at a floating gate doping of 3.1019 cm-3. A trade-off will be discussed.